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| v r 4181? 64-/32-bit microprocessor hardware ? ? ? ? nec electronics corporation 2000 ? ? ? ? mips technologies, inc. 1998 printed in japan document no. u14272ej3v0um00 (3rd edition) date published november 2002 ns cp(k) user?s manual pd30181
user?s manual u14272ej3v0um 2 [memo] user?s manual u14272ej3v0um 3 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. v r 10000, v r 12000, v r 4000, v r 4000 series, v r 4100, v r 4100 series, v r 4110, v r 4111, v r 4121, v r 4122, v r 4181, v r 4300, v r 4305, v r 4310, v r 4400, v r 5000a, v r 5432, and v r series are trademarks of nec electronics corporation. mips is a registered trademark of mips technologies, inc. in the united states. mba is a trademark of vadem corporation. pentium, intel, and strataflash are trademarks of intel corporation. dec vax is a trademark of digital equipment corporation. pc/at is a trademark of international business machines corporation. user ? s manual u14272ej3v0um 4 exporting this product or equipment that includes this product may require a governmental license from the u.s.a. for some countries because this product utilizes technologies limited by the export control regulations of the u.s.a. the information in this document is current as of january, 2002. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) (1) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. (2) "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). ? ? ? ? ? ? user ? s manual u14272ej3v0um 5 regional information ? ? ? ? ? ? sucursal en espa ? a madrid, spain tel: 091-504 27 87 fax: 091-504 28 60 v lizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 succursale fran ? aise filiale italiana milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 fax: 040-244 45 80 tyskland filial taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 united kingdom branch milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify: user?s manual u14272ej3v0um 6 major revisions in this edition (1/5) page description throughout this manual separation of the following parts of the previous (the 2nd) edition chapter 3 mips iii inst ruction set summary, chapter 4 mips16 instruction set, chapter 5 v r 4181 pipeline, chapter 6 memory management system (first half), chapter 7 exception processing (second half), chapter 9 cache memory, chapter 10 cpu core interrupts, chapter 27 mips iii inst ruction set details, chapter 28 mips16 instruction set format p. 30 deletion of modem block in figure 1-1. internal block diagram p. 34 modification of description in 1.3.16 lcd interface p. 35 modification of remark in 1.3.17 wake-up events pp. 38 to 42 addition of 1.4.2 cpu instruction set overview and 1.4.3 data formats and addressing p. 43 modification of description and deletion of figure in 1.4.4 cp0 registers pp. 45, 46 addition of 1.4.9 power modes and 1.4.10 code compatibility p. 47 addition of descriptions in 1.5 clock interface pp. 48, 49 addition of figure 1-8. external circuits of clock oscillator and figure 1-9. incorrect connection circuits of resonator p. 52 modification of note in 2.2.1 system bus interface signals p. 53 modification of descriptions for sysdir and sysen# and addition of description in note in 2.2.1 system bus interface signals p. 58 addition of description for irdin/rxd2 in 2.2.10 irda interface signals p. 60 addition and modification in 2.3 pin status in specific status pp. 63 to 66 addition of 2.4 recommended connection of unused pins and i/o circuit types and 2.5 pin i/o circuits pp. 67 to 90 addition of chapter 3 cp0 registers p. 95 modification of table 4-6. dram address map p. 97 modification of description in 5.1.1 rtc reset pp. 97 to 101, 104, 105 addition of description in note in figure 5-1 through figure 5-5 , figure 5-8 , and figure 5-9 p. 98 modification in figure 5-2. rstsw reset p. 101 modification of description in 5.1.5 haltimer shutdown p. 104 addition of description in 5.3.1 cold reset p. 105 modification of description in 5.3.2 soft reset pp. 106, 107 addition of 5.4 notes on initialization p. 108 modification in figure 6-1. v r 4181 internal bus structure p. 109 modification of description in 6.1.2 (3) lcd module (lcd control unit) p. 111 modification of description for bit 4 and addition of caution and remark in 6.2.1 bcucntreg1 (0x0a00 0000) p. 113 modification of descriptions for bits 14 to 12, bits 3 to 0, and remark in 6.2.3 bcuspeedreg (0x0a00 000c) p. 114 modification of figure 6-2. rom read cycle and access parameters p. 117 deletion of description for div4 mode and addition of description in remark in 6.2.6 (2) peripheral clock (tclock) user?s manual u14272ej3v0um 7 major revisions in this edition (2/5) page description p. 119 modification of description in 6.3.2 connection to external rom (x 16) devices p. 122 modification of remark in 6.3.3 (4) 64 mbit pagerom p. 123 modification of figure in 6.3.3 (5) 32 mbit flash memory (when using intel tm dd28f032) pp. 125 to 128, 130 modification of figure 6-3 through figure 6-8 p. 129 addition of description in table 6-2. v r 4181 edo dram capacity p. 134 addition of caution and modification in remark in 6.5.2 memcfg_reg (0x0a00 0304) p. 135 modification of description for bits 6 to 4 in 6.5.3 mode_reg (0x0a00 0308) p. 136 modification of note in 6.5.4 sdtimingreg (0x0a00 030c) p. 137 addition of description in 6.6 isa bridge p. 138 addition of description in 6.7.1 isabrgctl (0x0b00 02c0) p. 140 modification of description for bits 10 and 9 and addition of description in 6.7.3 xisactl (0x0b00 02c4) p. 149 modification of description for bits 3 and 2 in 7.2.6 aiudmamskreg (0x0a00 0046) p. 150 modification of values at reset in 7.2.7 micrclenreg (0x0a00 0658) and 7.2.8 spkrclenreg (0x0a00 065a) p. 151 addition of description for bit 8 in 7.2.9 micdmacfgreg (0x0a00 065e) p. 152 addition of description for bit 0 in 7.2.10 spkdmacfgreg (0x0a00 0660) p. 153 addition of description for bits 5 and 4 in 7.2.11 dmaitrqreg (0x0a00 0662) p. 156 modification of description and addition of caution in 8.1 overview p. 157 addition of caution in figure 8-1. sck and si/so relationship pp. 157, 158 addition and modification of descriptions in 8.2.2 sck phase and csi transfer timing p. 159 modification of description in 8.2.3 (1) burst mode pp. 161, 162 addition of remarks and description in 8.3.1 csimode (0x0b00 0900) p. 171 addition of description in 9.1 overview p. 173 modification of description in table 9-1. icu registers p. 184 modification of address and description for bits 2 and 1, and addition of description in 9.2.9 kiuintreg (0x0b00 0086) p. 186 modification of r/w and addition of description in 9.2.11 maiuintreg (0x0b00 0090) p. 189 modification of description in figure 10-1. transition of v r 4181 power mode pp. 190, 191 addition and modification of descriptions in 10.2.1 power mode and state transition p. 191 modification of description in table 10-2. operations during reset p. 192 modification of location of 10.3.3 deadman?s switch reset p. 192 modification of figure 10-2. edo dram signals on rstsw reset (sdram bit = 0) p. 192 modification of description in 10.3.4 (2) preserving sdram data p. 193 modification of description in table 10-3. operations during shutdown p. 194 modification of description of caution in 10.5 power-on control p. 196 modification of signal name in 10.5.2 activation via compactflash interrupt request p. 197 modification of description in 10.5.3 activation via gpio activation interrupt request user?s manual u14272ej3v0um 8 major revisions in this edition (3/5) page description p. 198 modification of description of cautions in 10.5.4 activation via dcd interrupt request pp. 201 to 204 modification of descriptions in 10.6.1 through 10.6.4 pp. 205 to 207 addition of 10.6.5 through 10.6.8 p. 209 modification of description for bit 6 in 10.7.1 pmuintreg (0x0b00 00a0) p. 211 modification of value at reset for bit 7 in 10.7.2 pmucntreg (0x0b00 00a2) p. 214 modification of description for bit 2 to 0 in 10.7.4 pmudivreg (0x0b00 00ac) p. 215 modification of description for bit 4 in 10.7.5 dramhibctl (0x0b00 00b2) p. 220 modification of value at reset for bit 15 in 11.2.2 (3) ecmphreg (0x0b00 00cc) p. 238 modification and addition of descriptions in 13.1.3 general-purpose registers p. 242 modification of description in 13.2.5 16-bit bus cycles p. 254 modification of r/w for bits 15 to 8 in 13.3.5 gpdathreg (0x0b00 0308) p. 267 modification of description in 13.3.15 keyen (0x0b00 031c) p. 270 modification of description for bit 15 in 13.3.19 pcs1stra (0x0b00 0326) p. 273 modification of description for bit 7 in 13.3.23 lcdgpmode (0x0b00 032e) p. 275 addition of caution in 14.1 general p. 283 modification of location of note in table 14-3. piucntreg bit manipulation and states p. 286 modification of description for bits 5 to 0 in 14.3.4 piustblreg (0x0b00 0128) p. 289 addition of description in 14.3.6 piuascnreg (0x0b00 0130) p. 290 modification of description in table 14-4. piuascnreg bit manipulation and states p. 291 addition of description in 14.3.7 piuamskreg (0x0b00 0132) p. 292 modification of values at reset for bits 2 to 0 in 14.3.8 piucivlreg (0x0b00 013e) p. 295 modification of description in table 14-7. mask clear during scan sequencer operation p. 298 addition of note in figure 14-6. touch/release detection timing p. 298 modification of figure 14-7. a/d port scan timing p. 301 modification of description and addition of caution in 15.1 general pp. 303, 304 modification of addresses in 15.2.1 sdmadatreg (0x0b00 0160) and 15.2.2 mdmadatreg (0x0b00 0162) p. 308 modification of values at reset for bits 11, 10 and 5 and addition of caution in 15.2.6 scnvc_end (0x0b00 016e) p. 314 modification of values at reset for bits 11, 10 and 5 and addition of caution in 15.2.12 mcnvc_end (0x0b00 017e) pp. 315, 316 addition of descriptions in 15.3.1 output (speaker) and 15.3.2 input (microphone) p. 320 modification of description in 16.2.6 interrupts and status reporting p. 321 modification of description in table 16-3. kiu interrupt registers p. 324 modification of description for bits 1 and 0 in 16.3.3 kiuscans (0x0b00 0192) p. 325 modification of descriptions for bits 14 to 10 and bits 4 to 0 in 16.3.4 kiuwks (0x0b00 0194) p. 327 modification and addition of descriptions for bits 2 to 0 in 16.3.6 kiuint (0x0b00 0198) p. 328 modification of signal name in 17.1 general user?s manual u14272ej3v0um 9 major revisions in this edition (4/5) page description p. 333 modification of signal names in figure 17-1. compactflash interrupt logic p. 333 modification of description for bit 0 in 17.3.3 cfg_reg_1 (0x0b00 08fe) p. 336 addition of caution for bit 4 in 17.4.3 pwrrsetdrv (index: 0x02) p. 337 modification of description for bit 7 in 17.4.4 itgencreg (index: 0x03) p. 338 modification of description and addition of caution for bit 0 in 17.4.5 cdstchgreg (index: 0x04) p. 341 modification of descriptions for bits 7, 4, 3, and 0 in 17.4.8 ioctrl_reg (index: 0x07) p. 344 modification of description for bit 6 in 17.4.14 memwidn_reg (index: 0x11, 0x19, 0x21, 0x29, 0x31) p. 345 modification of description for bits 7 and 6 and addition of description in 17.4.16 memseln_reg (index: 0x13, 0x1b, 0x23, 0x2b, 0x33) p. 346 addition of description in 17.4.17 memofflnreg (index: 0x14, 0x1c, 0x24, 0x2c, 0x34) p. 346 modification of remark for bits 5 to 0 in 17.4.18 memoffhnreg (index: 0x15, 0x1d, 0x25, 0x2d, 0x35) p. 348 modification of description for bit 2 in 17.4.20 gloctrlreg (index: 0x1e) p. 349 modification of description for bits 1 and 0 and addition of description in 17.4.22 voltselreg (index: 0x2f) pp. 350, 351 addition of 17.5 memory mapping of compactflash card p. 352 addition of 17.6 controlling bus when compactflash card is used p. 356 addition of function for bit 2 in 18.2.3 ledcntreg (0x0b00 0248) p. 357 modification of description in 18.2.4 ledastcreg (0x0b00 024a) p. 359 modification of figure in 18.3 operation flow p. 360 addition of caution in 19.1 general p. 361 modification of description in table 19-1. siu1 registers pp. 362, 364, 376 modification of values at reset in 19.3.1 through 19.3.3 , 19.3.5 , and 19.3.12 p. 365 addition of description in table 19-2. correspondence between baud rates and divisors p. 368 modification of descriptions for bits 2 to 0 in 19.3.7 siufc_1 (0x0c00 0012: write) p. 373 modification of r/w and addition of description in 19.3.10 siuls_1 (0x0c00 0015) p. 375 modification of descriptions for bits 7 to 4 in 19.3.11 siums_1 (0x0c00 0016) p. 377 modification of r/w for bit 1 in 19.3.14 siuactmsk_1 (0x0c00 001c) p. 379 addition of description and caution in 20.1 general p. 380 modification of description in table 20-1. siu2 registers pp. 381, 383, 395 modification of values at reset in 20.3.1 through 20.3.3 , 20.3.5 , and 20.3.12 p. 384 addition of description in table 20-2. correspondence between baud rates and divisors p. 387 modification of descriptions for bits 2 to 0 in 20.3.7 siufc_2 (0x0c00 0002: write) p. 392 modification of r/w and addition of description in 20.3.10 siuls_2 (0x0c00 0005) p. 394 modification of descriptions for bits 7 to 4 in 20.3.11 siums_2 (0x0c00 0006) p. 395 addition of description in 20.3.13 siuirsel_2 (0x0c00 008) p. 397 modification of r/w for bit 1 in 20.3.16 siuactmsk_2 (0x0c00 000c) user?s manual u14272ej3v0um 10 major revisions in this edition (5/5) page description p. 399 modification of description in 21.1.1 lcd interface p. 401 modification of bus width in figure 21-1. lcd controller block diagram p. 406 modification of description in 21.3.4 frame buffer memory and fifo p. 420 addition of remark in 21.4.11 lcdcfgreg0 (0x0a00 0414) p. 428 addition of remark in 21.4.22 cpindctreg (0x0a00 047e) p. 429 addition of caution in 21.4.23 cpaldatreg (0x0a00 0480) p. 433 addition of caution in table 23-1. coprocessor 0 hazards pp. 436 to 438 addition of appendix a restrictions on v r 4181 pp. 439 to 444 addition of appendix b index the mark shows major revised points. user?s manual u14272ej3v0um 11 preface readers this manual targets users who intend to understand the functions of the v r 4181 and to design application systems using this microprocessor. purpose this manual introduces the hardware functions of the v r 4181 to users, following the organization described below. organization two manuals are available for the v r 4181: hardware user?s manual (this manual) and architecture user?s manual common to the v r 4100 series tm . hardware user?s manual architecture user?s manual pin functions physical address space function of coprocessor 0 initialization interface peripheral units pipeline operation cache organization and memory management system exception processing interrupts instruction set how to read this manual it is assumed that the reader of this manual has general knowledge in the fields of electric engineering, logic circuits, microcomputers, and sdrams. to learn about the overall functions of the v r 4181, read this manual in sequential order. to learn about instruction sets, read v r 4100 series architecture user?s manual that is separately available. to learn about electrical specifications, refer to data sheet that is separately available. conventions data significance: higher on left and lower on right active low: xxx# (trailing # after pin and signal names) note : description of item marked with note in the text caution : information requiring particular attention remark : supplementary information numeric representation: binary/decimal ... xxxx hexadecimal ... 0xxxxx prefixes representing an exponent of 2 (for address space or memory capacity): k (kilo) ? 2 10 = 1024 m (mega) ? 2 20 = 1024 2 g (giga) ? 2 30 = 1024 3 t (tera) ? 2 40 = 1024 4 p (peta) ? 2 50 = 1024 5 e (exa) ? 2 60 = 1024 6 user?s manual u14272ej3v0um 12 related documents when using this manual, also refer to the following documents. document name document number v r 4181 hardware user?s manual this manual pd30181 (v r 4181) data sheet u14273e v r 4100 series architecture user?s manual u15509e v r series tm programming guide application note u10710e the related documents indicated here may include preliminary version. however, preliminary versions are not marked as such. user?s manual u14272ej3v0um 13 contents chapter 1 introduction ..................................................................................................... ........ 29 1.1 features ................................................................................................................. ................... 29 1.2 ordering information ..................................................................................................... .......... 30 1.3 v r 4181 key features ............................................................................................................. .. 30 1.3.1 cpu core ............................................................................................................... ...................... 31 1.3.2 bus interface .......................................................................................................... ..................... 31 1.3.3 memory interface ....................................................................................................... .................. 32 1.3.4 dma controller (dcu) ................................................................................................... ............... 32 1.3.5 interrupt controller (icu) ............................................................................................. ................. 32 1.3.6 real-time clock ........................................................................................................ .................... 32 1.3.7 audio output (d/a converter) ........................................................................................... ............ 32 1.3.8 touch panel interface and audio input (a/d converter) ............................................................... 32 1.3.9 compactflash interface (ecu) ........................................................................................... ........ 32 1.3.10 serial interface channel 1 (siu1) ..................................................................................... ......... 32 1.3.11 serial interface channel 2 (siu2) ..................................................................................... ......... 32 1.3.12 clocked serial interface (csi) ........................................................................................ ............ 33 1.3.13 keyboard interface (kiu) .............................................................................................. ............. 33 1.3.14 general-purpose i/o ................................................................................................... ............... 33 1.3.15 programmable chip selects ............................................................................................. .......... 34 1.3.16 lcd interface ......................................................................................................... ................... 34 1.3.17 wake-up events ........................................................................................................ ................ 35 1.4 v r 4110 cpu core ................................................................................................................. .... 35 1.4.1 cpu registers .......................................................................................................... .................... 37 1.4.2 cpu instruction set overview ........................................................................................... ........... 38 1.4.3 data formats and addressing ............................................................................................ .......... 40 1.4.4 cp0 registers .......................................................................................................... ..................... 43 1.4.5 floating-point unit (fpu) .............................................................................................. ............... 44 1.4.6 memory management unit ................................................................................................. .......... 44 1.4.7 cache .................................................................................................................. ........................ 44 1.4.8 instruction pipeline ................................................................................................... ................... 44 1.4.9 power modes ............................................................................................................ .................. 45 1.4.10 code compatibility .................................................................................................... ................. 46 1.5 clock interface .......................................................................................................... ............... 47 chapter 2 pin functions ................................................................................................... ......... 50 2.1 pin configuration ........................................................................................................ ............. 50 2.2 pin function description ................................................................................................. ....... 52 2.2.1 system bus interface signals ........................................................................................... ............ 52 2.2.2 lcd interface signals .................................................................................................. ................ 54 2.2.3 initialization interface signals ....................................................................................... ............... 55 2.2.4 battery monitor interface signals ...................................................................................... ........... 55 2.2.5 clock interface signals ................................................................................................ ................ 55 2.2.6 touch panel interface and audio interface signals ...................................................................... 56 user?s manual u14272ej3v0um 14 2.2.7 led interface signals .................................................................................................. ................. 56 2.2.8 compactflash interface and keyboard interface signals ............................................................. 56 2.2.9 serial interface channel 1 signals ..................................................................................... ........... 57 2.2.10 irda interface signals ................................................................................................ ................ 58 2.2.11 general-purpose i/o signals ........................................................................................... ........... 58 2.2.12 dedicated v dd /gnd signals ...................................................................................................... 59 2.3 pin status in specific status ............................................................................................ ...... 60 2.4 recommended connection of unused pins and i/o circuit types .................................... 63 2.5 pin i/o circuits ......................................................................................................... ................ 66 chapter 3 cp0 registers ................................................................................................... ......... 67 3.1 coprocessor 0 (cp0) ...................................................................................................... ......... 67 3.2 details of cp0 registers ................................................................................................. ........ 69 3.2.1 index register (0) ..................................................................................................... .................... 69 3.2.2 random register (1) .................................................................................................... ................. 69 3.2.3 entrylo0 (2) and entrylo1 (3) registers ................................................................................ ...... 70 3.2.4 context register (4) ................................................................................................... ................... 71 3.2.5 pagemask register (5) .................................................................................................. ............... 72 3.2.6 wired register (6) ..................................................................................................... .................... 73 3.2.7 badvaddr register (8) .................................................................................................. ................ 74 3.2.8 count register (9) ..................................................................................................... .................... 74 3.2.9 entryhi register (10) .................................................................................................. .................. 75 3.2.10 compare register (11) ................................................................................................. .............. 76 3.2.11 status register (12) .................................................................................................. .................. 76 3.2.12 cause register (13) ................................................................................................... ................. 79 3.2.13 exception program counter (epc) register (14) ....................................................................... 81 3.2.14 processor revision identifier (prid) register (15) .................................................................... .82 3.2.15 config register (16) .................................................................................................. .................. 83 3.2.16 load linked address (lladdr) register (17) ............................................................................ .84 3.2.17 watchlo (18) and watchhi (19) registers ............................................................................... .. 85 3.2.18 xcontext register (20) ................................................................................................ ............... 86 3.2.19 parity error register (26) ............................................................................................ ................ 87 3.2.20 cache error register (27) ............................................................................................. .............. 87 3.2.21 taglo (28) and taghi (29) registers ................................................................................... ...... 88 3.2.22 errorepc register (30) ................................................................................................ ............... 89 chapter 4 memory management system ............................................................................ 91 4.1 overview ................................................................................................................. .................. 91 4.2 physical address space ................................................................................................... ...... 92 4.2.1 rom space .............................................................................................................. .................... 93 4.2.2 external system bus space .............................................................................................. ............ 93 4.2.3 internal i/o space ..................................................................................................... ................... 94 4.2.4 dram space ............................................................................................................. .................. 95 user?s manual u14272ej3v0um 15 chapter 5 initialization interface ....................................................................................... 9 6 5.1 reset function ........................................................................................................... .............. 96 5.1.1 rtc reset .............................................................................................................. ...................... 97 5.1.2 rstsw reset ............................................................................................................ .................. 98 5.1.3 deadman?s switch reset ................................................................................................. ............. 99 5.1.4 software shutdown ...................................................................................................... ................ 100 5.1.5 haltimer shutdown ...................................................................................................... .............. 101 5.2 power-on sequence ........................................................................................................ ........ 102 5.3 reset of cpu core ........................................................................................................ ........... 104 5.3.1 cold reset ............................................................................................................. ...................... 104 5.3.2 soft reset ............................................................................................................. ....................... 105 5.4 notes on initialization .................................................................................................. ........... 106 5.4.1 cpu core ............................................................................................................... ...................... 106 5.4.2 internal peripheral units .............................................................................................. ................. 106 5.4.3 returning from power mode .............................................................................................. .......... 107 chapter 6 bus control ..................................................................................................... ......... 108 6.1 mba host bridge .......................................................................................................... ........... 108 6.1.1 mba host bridge rom and register address space ................................................................... 109 6.1.2 mba modules address space .............................................................................................. ........ 109 6.2 bus control registers .................................................................................................... ......... 110 6.2.1 bcucntreg1 (0x0a00 0000) ............................................................................................... .... 111 6.2.2 cmuclkmsk (0x0a00 0004) ................................................................................................ ..... 112 6.2.3 bcuspeedreg (0x0a00 000c) .............................................................................................. .. 113 6.2.4 bcurfcntreg (0x0a00 0010) .............................................................................................. .. 115 6.2.5 revidreg (0x0a00 0014) ................................................................................................. ........ 116 6.2.6 clkspeedreg (0x0a00 0018) .............................................................................................. ... 117 6.3 rom interface ............................................................................................................ .............. 118 6.3.1 external rom devices memory mapping .................................................................................... 118 6.3.2 connection to external rom (x 16) devices .............................................................................. .. 119 6.3.3 example of rom connection .............................................................................................. ......... 120 6.3.4 external rom cycles .................................................................................................... ............... 125 6.4 dram interface ........................................................................................................... ............. 128 6.4.1 edo dram configuration ................................................................................................. ........... 128 6.4.2 mixed memory mode (edo dram only) ..................................................................................... 1 29 6.4.3 edo dram timing parameters ............................................................................................. ...... 129 6.4.4 sdram configuration .................................................................................................... .............. 130 6.5 memory controller register set ........................................................................................... .. 131 6.5.1 edomcytreg (0x0a00 0300) ............................................................................................... ... 131 6.5.2 memcfg_reg (0x0a00 0304) ............................................................................................... ... 133 6.5.3 mode_reg (0x0a00 0308) ................................................................................................. ...... 135 6.5.4 sdtimingreg (0x0a00 030c) .............................................................................................. .... 136 6.6 isa bridge ............................................................................................................... ................. 137 user?s manual u14272ej3v0um 16 6.7 isa bridge register set .................................................................................................. ......... 137 6.7.1 isabrgctl (0x0b00 02c0) ................................................................................................ ....... 138 6.7.2 isabrgsts (0x0b00 02c2) ................................................................................................ ....... 139 6.7.3 xisactl (0x0b00 02c4) .................................................................................................. ........... 140 chapter 7 dma control unit (dcu) ....................................................................................... 1 42 7.1 general .................................................................................................................. .................... 142 7.2 dcu registers ........................................................................................................... .............. 144 7.2.1 microphone destination 1 address registers ............................................................................. ... 145 7.2.2 microphone destination 2 address registers ............................................................................. ... 146 7.2.3 speaker source 1 address registers ..................................................................................... ....... 147 7.2.4 speaker source 2 address registers ..................................................................................... ....... 148 7.2.5 dmarstreg (0x0a00 0040) ................................................................................................ ..... 149 7.2.6 aiudmamskreg (0x0a00 0046) ............................................................................................. .. 149 7.2.7 micrclenreg (0x0a00 0658) .............................................................................................. .... 150 7.2.8 spkrclenreg (0x0a00 065a) .............................................................................................. ... 150 7.2.9 micdmacfgreg (0x0a00 065e) ............................................................................................. . 151 7.2.10 spkdmacfgreg (0x0a00 0660) ............................................................................................ 152 7.2.11 dmaitrqreg (0x0a00 0662) .............................................................................................. .... 153 7.2.12 dmactlreg (0x0a00 0664) ............................................................................................... ..... 154 7.2.13 dmaitmkreg (0x0a00 0666) .............................................................................................. .... 155 chapter 8 clocked serial interface unit (csi) ............................................................. 156 8.1 overview ................................................................................................................. .................. 156 8.2 operation of csi ......................................................................................................... .............. 156 8.2.1 transmit/receive operations ............................................................................................ ............ 156 8.2.2 sck phase and csi transfer timing ...................................................................................... ....... 157 8.2.3 csi transfer types ..................................................................................................... ................... 159 8.2.4 transmit and receive fifos ............................................................................................. ........... 160 8.3 csi registers ............................................................................................................ ................ 160 8.3.1 csimode (0x0b00 0900) .................................................................................................. ......... 161 8.3.2 csirxdata (0x0b00 0902) ................................................................................................ ........ 163 8.3.3 csitxdata (0x0b00 0904) ................................................................................................ ........ 163 8.3.4 csilstat (0x0b00 0906) ................................................................................................. .......... 164 8.3.5 csiintmsk (0x0b00 0908) ................................................................................................ ......... 166 8.3.6 csiintstat (0x0b00 090a) ............................................................................................... ........ 167 8.3.7 csitxblen (0x0b00 090c) ................................................................................................ ........ 169 8.3.8 csirxblen (0x0b00 090e) ................................................................................................ ....... 170 chapter 9 interrupt control unit (icu) ............................................................................ 171 9.1 overview ................................................................................................................. .................. 171 9.2 register set ............................................................................................................. ................. 173 9.2.1 sysint1reg (0x0a00 0080) ............................................................................................... ...... 174 9.2.2 msysint1reg (0x0a00 008c) .............................................................................................. .... 176 9.2.3 nmireg (0x0a00 0098) ................................................................................................... ........... 178 user?s manual u14272ej3v0um 17 9.2.4 softintreg (0x0a00 009a) ............................................................................................... ..... 179 9.2.5 sysint2reg (0x0a00 0200) ............................................................................................... ...... 180 9.2.6 msysint2reg (0x0a00 0206) .............................................................................................. .... 181 9.2.7 piuintreg (0x0b00 0082) ................................................................................................ ........ 182 9.2.8 aiuintreg (0x0b00 0084) ................................................................................................ ........ 183 9.2.9 kiuintreg (0x0b00 0086) ................................................................................................ ........ 184 9.2.10 mpiuintreg (0x0b00 008e) .............................................................................................. ..... 185 9.2.11 maiuintreg (0x0b00 0090) .............................................................................................. ..... 186 9.2.12 mkiuintreg (0x0b00 0092) .............................................................................................. ..... 187 chapter 10 power management unit (pmu) ...................................................................... 188 10.1 general ................................................................................................................. .................. 188 10.2 v r 4181 power mode .............................................................................................................. 1 88 10.2.1 power mode and state transition ....................................................................................... ........ 188 10.3 reset control ........................................................................................................... .............. 191 10.3.1 rtc reset ............................................................................................................. ..................... 191 10.3.2 rstsw reset ........................................................................................................... ................. 192 10.3.3 deadman?s switch reset ................................................................................................ ............ 192 10.3.4 preserving dram data on rstsw reset .................................................................................. 1 92 10.4 shutdown control ........................................................................................................ ......... 193 10.4.1 haltimer shutdown ..................................................................................................... ............. 193 10.4.2 software shutdown ..................................................................................................... ............... 193 10.4.3 battinh shutdown ...................................................................................................... ............. 193 10.5 power-on control ........................................................................................................ ........... 194 10.5.1 activation via power switch interrupt request ......................................................................... .. 195 10.5.2 activation via compactflash interrupt request ......................................................................... . 196 10.5.3 activation via gpio activation interrupt request ...................................................................... .. 197 10.5.4 activation via dcd interrupt request .................................................................................. ....... 198 10.5.5 activation via elapsedtime (rtc alarm) interrupt request ....................................................... 200 10.6 dram interface control .................................................................................................. ...... 201 10.6.1 entering hibernate mode (edo dram) .................................................................................... 201 10.6.2 entering hibernate mode (sdram) ....................................................................................... ... 202 10.6.3 exiting hibernate mode (edo dram) ..................................................................................... . 203 10.6.4 exiting hibernate mode (sdram) ........................................................................................ ..... 204 10.6.5 entering suspend mode (edo dram) ..................................................................................... 2 05 10.6.6 entering suspend mode (sdram) ......................................................................................... ... 206 10.6.7 exiting suspend mode (edo dram) ....................................................................................... . 207 10.6.8 exiting suspend mode (sdram) .......................................................................................... .... 207 10.7 register set ............................................................................................................ ................ 208 10.7.1 pmuintreg (0x0b00 00a0) ............................................................................................... ..... 209 10.7.2 pmucntreg (0x0b00 00a2) ............................................................................................... ... 211 10.7.3 pmuwaitreg (0x0b00 00a8) .............................................................................................. ... 213 10.7.4 pmudivreg (0x0b00 00ac) ............................................................................................... .... 214 10.7.5 dramhibctl (0x0b00 00b2) .............................................................................................. .... 215 user?s manual u14272ej3v0um 18 chapter 11 realtime clock unit (rtc) ................................................................................ 216 11.1 general ................................................................................................................. ................... 216 11.2 register set ............................................................................................................ ................ 216 11.2.1 elapsedtime registers ................................................................................................. .............. 217 11.2.2 elapsedtime compare registers ......................................................................................... ....... 219 11.2.3 rtclong1 registers .................................................................................................... .............. 221 11.2.4 rtclong1 count registers .............................................................................................. ........... 223 11.2.5 rtclong2 registers .................................................................................................... .............. 225 11.2.6 rtclong2 count registers .............................................................................................. ........... 227 11.2.7 rtc interrupt register ................................................................................................ ................ 229 chapter 12 deadman?s switch unit (dsu) ........................................................................... 230 12.1 general ................................................................................................................. ................... 230 12.2 register set ............................................................................................................ ................ 230 12.2.1 dsucntreg (0x0b00 00e0) ............................................................................................... .... 231 12.2.2 dsusetreg (0x0b00 00e2) ............................................................................................... .... 232 12.2.3 dsuclrreg (0x0b00 00e4) ............................................................................................... .... 233 12.2.4 dsutimreg (0x0b00 00e6) ............................................................................................... ..... 234 12.3 register setting flow ................................................................................................... ......... 235 chapter 13 general purpose i/o unit (giu) ...................................................................... 236 13.1 overview ................................................................................................................ ................. 236 13.1.1 gpio pins and alternate functions ..................................................................................... ........ 236 13.1.2 i/o direction control ................................................................................................. .................. 238 13.1.3 general-purpose registers ............................................................................................. ............ 238 13.2 alternate functions overview ............................................................................................ .. 238 13.2.1 clocked serial interface (csi) ........................................................................................ ............ 238 13.2.2 serial interface channels 1 and 2 ..................................................................................... ......... 239 13.2.3 lcd interface ......................................................................................................... .................... 241 13.2.4 programmable chip selects ............................................................................................. .......... 242 13.2.5 16-bit bus cycles ..................................................................................................... ................... 242 13.2.6 general purpose input/output .......................................................................................... .......... 242 13.2.7 interrupt requests and wake-up events ................................................................................. .... 243 13.3 register set ............................................................................................................ ................ 244 13.3.1 gpmd0reg (0x0b00 0300) ................................................................................................ ...... 246 13.3.2 gpmd1reg (0x0b00 0302) ................................................................................................ ...... 248 13.3.3 gpmd2reg (0x0b00 0304) ................................................................................................ ...... 250 13.3.4 gpmd3reg (0x0b00 0306) ................................................................................................ ...... 252 13.3.5 gpdathreg (0x0b00 0308) ............................................................................................... .... 254 13.3.6 gpdatlreg (0x0b00 030a) ............................................................................................... ..... 255 13.3.7 gpinten (0x0b00 030c) ................................................................................................. ......... 256 13.3.8 gpintmsk (0x0b00 030e) ................................................................................................ ....... 257 13.3.9 gpinttyph (0x0b00 0310) ............................................................................................... ....... 258 13.3.10 gpinttypl (0x0b00 0312) .............................................................................................. ...... 260 13.3.11 gpintstat (0x0b00 0314) .............................................................................................. ...... 262 user?s manual u14272ej3v0um 19 13.3.12 gphibsth (0x0b00 0316) ............................................................................................... ....... 263 13.3.13 gphibstl (0x0b00 0318) ............................................................................................... ....... 264 13.3.14 gpsictl (0x0b00 031a) ................................................................................................ ........ 265 13.3.15 keyen (0x0b00 031c) .................................................................................................. ......... 267 13.3.16 pcs0stra (0x0b00 0320) ............................................................................................... ...... 268 13.3.17 pcs0stpa (0x0b00 0322) ............................................................................................... ...... 268 13.3.18 pcs0hia (0x0b00 0324) ................................................................................................ ........ 269 13.3.19 pcs1stra (0x0b00 0326) ............................................................................................... ...... 270 13.3.20 pcs1stpa (0x0b00 0328) ............................................................................................... ...... 270 13.3.21 pcs1hia (0x0b00 032a) ................................................................................................ ........ 271 13.3.22 pcsmode (0x0b00 032c) ................................................................................................ ..... 272 13.3.23 lcdgpmode (0x0b00 032e) .............................................................................................. .. 273 13.3.24 miscregn (0x0b00 0330 to 0x0b00 034e) ........................................................................... 274 chapter 14 touch panel interface unit (piu) ................................................................. 275 14.1 general ................................................................................................................. .................. 275 14.1.1 block diagrams ........................................................................................................ .................. 276 14.2 scan sequencer state transition ......................................................................................... 278 14.3 register set ............................................................................................................ ................ 280 14.3.1 piucntreg (0x0b00 0122) ............................................................................................... ...... 281 14.3.2 piuintreg (0x0b00 0124) ............................................................................................... ....... 284 14.3.3 piusivlreg (0x0b00 0126) .............................................................................................. ...... 285 14.3.4 piustblreg (0x0b00 0128) .............................................................................................. ..... 286 14.3.5 piucmdreg (0x0b00 012a) ............................................................................................... ..... 287 14.3.6 piuascnreg (0x0b00 0130) .............................................................................................. .... 289 14.3.7 piuamskreg (0x0b00 0132) .............................................................................................. .... 291 14.3.8 piucivlreg (0x0b00 013e) .............................................................................................. ...... 292 14.3.9 piupbnmreg (0x0b00 02a0 to 0x0b00 02ae, 0x0b00 02bc to 0x0b00 02be) .................... 293 14.3.10 piuabnreg (0x0b00 02b0 to 0x0b00 02b6) ........................................................................ 294 14.4 state transition flow ................................................................................................... ......... 295 14.5 relationships among tpx, tpy, adin, and audioin pins and states ............................ 297 14.6 timing .................................................................................................................. ................... 298 14.6.1 touch/release detection timing ........................................................................................ ......... 298 14.6.2 a/d port scan timing .................................................................................................. ................ 298 14.7 data loss conditions .................................................................................................... ........ 299 chapter 15 audio interface unit (aiu) ................................................................................ 301 15.1 general ................................................................................................................. .................. 301 15.2 register set ............................................................................................................ ................ 302 15.2.1 sdmadatreg (0x0b00 0160) .............................................................................................. ... 303 15.2.2 mdmadatreg (0x0b00 0162) .............................................................................................. .. 304 15.2.3 davref_setup (0x0b00 0164) ............................................................................................ . 305 15.2.4 sodatreg (0x0b00 0166) ................................................................................................ ...... 306 15.2.5 scntreg (0x0b00 0168) ................................................................................................. ....... 307 15.2.6 scnvc_end (0x0b00 016e) ............................................................................................... .... 308 15.2.7 midatreg (0x0b00 0170) ................................................................................................ ....... 309 user?s manual u14272ej3v0um 20 15.2.8 mcntreg (0x0b00 0172) ................................................................................................. ....... 310 15.2.9 dvalidreg (0x0b00 0178) ............................................................................................... ...... 311 15.2.10 seqreg (0x0b00 017a) ................................................................................................. ....... 312 15.2.11 intreg (0x0b00 017c) ................................................................................................. ......... 313 15.2.12 mcnvc_end (0x0b00 017e) .............................................................................................. ... 314 15.3 operation sequence ..................................................................................................... ........ 315 15.3.1 output (speaker) ...................................................................................................... .................. 315 15.3.2 input (microphone) .................................................................................................... ................ 316 chapter 16 keyboard interface unit (kiu) ....................................................................... 317 16.1 general ................................................................................................................. ................... 317 16.2 functional description .................................................................................................. ........ 317 16.2.1 automatic keyboard scan mode (auto scan mode) .................................................................. 318 16.2.2 manual keyboard scan mode (manual scan mode) .................................................................. 318 16.2.3 key press detection ................................................................................................... ................ 318 16.2.4 scan operation ........................................................................................................ .................. 319 16.2.5 reading scanned data .................................................................................................. ............. 320 16.2.6 interrupts and status reporting ....................................................................................... ............ 320 16.3 register set ............................................................................................................ ................ 321 16.3.1 kiudatn (0x0b00 0180 to 0x0b00 018e) ................................................................................ 32 2 16.3.2 kiuscanrep (0x0b00 0190) .............................................................................................. ..... 323 16.3.3 kiuscans (0x0b00 0192) ................................................................................................ ........ 324 16.3.4 kiuwks (0x0b00 0194) .................................................................................................. .......... 325 16.3.5 kiuwki (0x0b00 0196) .................................................................................................. ........... 326 16.3.6 kiuint (0x0b00 0198) .................................................................................................. ............ 327 chapter 17 compactflash controller (ecu) .................................................................. 328 17.1 general ................................................................................................................. ................... 328 17.2 register set summary .................................................................................................... ....... 328 17.3 ecu control registers ................................................................................................... ....... 331 17.3.1 intstatreg (0x0b00 08f8) .............................................................................................. ..... 331 17.3.2 intmskreg (0x0b00 08fa) ............................................................................................... ..... 332 17.3.3 cfg_reg_1 (0x0b00 08fe) ............................................................................................... ..... 333 17.4 ecu registers ........................................................................................................... ............. 334 17.4.1 id_rev_reg (index: 0x00) .............................................................................................. ........ 334 17.4.2 if_stat_reg (index: 0x01) ............................................................................................. ........ 335 17.4.3 pwrrsetdrv (index: 0x02) .............................................................................................. ..... 336 17.4.4 itgenctreg (index: 0x03) .............................................................................................. ....... 337 17.4.5 cdstchgreg (index: 0x04) .............................................................................................. ..... 338 17.4.6 crdstatreg (index: 0x05) .............................................................................................. ...... 339 17.4.7 adwinenreg (index: 0x06) .............................................................................................. ...... 340 17.4.8 ioctrl_reg (index: 0x07) .............................................................................................. ........ 341 17.4.9 ioadslbnreg (index: 0x08, 0x0c) ....................................................................................... .. 342 17.4.10 ioadshbnreg (index: 0x09, 0x0d) ...................................................................................... 342 17.4.11 ioslbnreg (index: 0x0a, 0x0e) ........................................................................................ .... 343 17.4.12 ioshbnreg (index: 0x0b, 0x0f) ........................................................................................ ... 343 user?s manual u14272ej3v0um 21 17.4.13 sysmemslnreg (index: 0x10, 0x18, 0x20, 0x28, 0x30) ...................................................... 344 17.4.14 memwidn_reg (index: 0x11, 0x19, 0x21, 0x29, 0x31) ........................................................ 344 17.4.15 sysmemelnreg (index: 0x12, 0x1a, 0x22, 0x2a, 0x32) ..................................................... 345 17.4.16 memseln_reg (index: 0x13, 0x1b, 0x23, 0x2b, 0x33) ........................................................ 345 17.4.17 memofflnreg (index: 0x14, 0x1c, 0x24, 0x2c, 0x34) ....................................................... 346 17.4.18 memoffhnreg (index: 0x15, 0x1d, 0x25, 0x2d, 0x35) ...................................................... 346 17.4.19 dtgenclreg (index: 0x16) ............................................................................................. ..... 347 17.4.20 gloctrlreg (index: 0x1e) ............................................................................................. .... 348 17.4.21 voltsenreg (index: 0x1f) ............................................................................................. ..... 348 17.4.22 voltselreg (index: 0x2f) ............................................................................................. ..... 349 17.5 memory mapping of compactflash card ............................................................................ 350 17.6 controlling bus when compactflash card is used .......................................................... 352 17.6.1 controlling bus size .................................................................................................. ................. 352 17.6.2 controlling wait ...................................................................................................... .................... 352 chapter 18 led control unit (led) ...................................................................................... 3 53 18.1 general ................................................................................................................. .................. 353 18.2 register set ............................................................................................................ ................ 353 18.2.1 ledhtsreg (0x0b00 0240) ............................................................................................... ..... 354 18.2.2 ledltsreg (0x0b00 0242) ............................................................................................... ...... 355 18.2.3 ledcntreg (0x0b00 0248) ............................................................................................... ..... 356 18.2.4 ledastcreg (0x0b00 024a) .............................................................................................. ... 357 18.2.5 ledintreg (0x0b00 024c) ............................................................................................... ...... 358 18.3 operation flow .......................................................................................................... ............. 359 chapter 19 serial interface unit 1 (siu1) ........................................................................ 360 19.1 general ................................................................................................................. .................. 360 19.2 clock control logic ..................................................................................................... .......... 360 19.3 register set ............................................................................................................ ................ 361 19.3.1 siurb_1 (0x0c00 0010: lcr7 = 0, read) ............................................................................... 36 2 19.3.2 siuth_1 (0x0c00 0010: lcr7 = 0, write) ............................................................................... 3 62 19.3.3 siudll_1 (0x0c00 0010: lcr7 = 1) ...................................................................................... .. 362 19.3.4 siuie_1 (0x0c00 0011: lcr7 = 0) ....................................................................................... .... 363 19.3.5 siudlm_1 (0x0c00 0011: lcr7 = 1) ...................................................................................... . 364 19.3.6 siuiid_1 (0x0c00 0012: read) .......................................................................................... ...... 366 19.3.7 siufc_1 (0x0c00 0012: write) .......................................................................................... ...... 368 19.3.8 siulc_1 (0x0c00 0013) ................................................................................................. .......... 371 19.3.9 siumc_1 (0x0c00 0014) ................................................................................................. ......... 372 19.3.10 siuls_1 (0x0c00 0015) ................................................................................................ ......... 373 19.3.11 siums_1 (0x0c00 0016) ................................................................................................ ........ 375 19.3.12 siusc_1 (0x0c00 0017) ................................................................................................ ......... 376 19.3.13 siureset_1 (0x0c00 0019) ............................................................................................. ..... 376 19.3.14 siuactmsk_1 (0x0c00 001c) ............................................................................................ .. 377 19.3.15 siuacttmr_1 (0x0c00 001e) ............................................................................................ .. 378 user?s manual u14272ej3v0um 22 chapter 20 serial interface unit 2 (siu2) ......................................................................... 379 20.1 general ................................................................................................................. ................... 379 20.2 clock control logic ..................................................................................................... .......... 379 20.3 register set ............................................................................................................ ................ 380 20.3.1 siurb_2 (0x0c00 0000: lcr7 = 0, read) ............................................................................... 38 1 20.3.2 siuth_2 (0x0c00 0000: lcr7 = 0, write) ............................................................................... 3 81 20.3.3 siudll_2 (0x0c00 0000: lcr7 = 1) ...................................................................................... .. 381 20.3.4 siuie_2 (0x0c00 0001: lcr7 = 0) ....................................................................................... .... 382 20.3.5 siudlm_2 (0x0c00 0001: lcr7 = 1) ...................................................................................... . 383 20.3.6 siuiid_2 (0x0c00 0002: read) .......................................................................................... ....... 385 20.3.7 siufc_2 (0x0c00 0002: write) .......................................................................................... ....... 387 20.3.8 siulc_2 (0x0c00 0003) ................................................................................................. .......... 390 20.3.9 siumc_2 (0x0c00 0004) ................................................................................................. ......... 391 20.3.10 siuls_2 (0x0c00 0005) ................................................................................................ ......... 392 20.3.11 siums_2 (0x0c00 0006) ................................................................................................ ......... 394 20.3.12 siusc_2 (0x0c00 0007) ................................................................................................ ......... 395 20.3.13 siuirsel_2 (0x0c00 0008) ............................................................................................. ....... 395 20.3.14 siureset_2 (0x0c00 0009) ............................................................................................. ..... 396 20.3.15 siucsel_2 (0x0c00 000a) .............................................................................................. ...... 396 20.3.16 siuactmsk_2 (0x0c00 000c) ............................................................................................ .. 397 20.3.17 siuacttmr_2 (0x0c00 000e) ............................................................................................ ... 398 chapter 21 lcd controller ................................................................................................. .... 399 21.1 overview ................................................................................................................ ................. 399 21.1.1 lcd interface ......................................................................................................... .................... 399 21.2 lcd module features ..................................................................................................... ....... 400 21.3 lcd controller specification ............................................................................................ .... 402 21.3.1 panel configuration and interface ..................................................................................... ......... 402 21.3.2 controller clocks ..................................................................................................... ................... 405 21.3.3 palette ............................................................................................................... ........................ 406 21.3.4 frame buffer memory and fifo .......................................................................................... ...... 406 21.3.5 panel power on/off sequence ........................................................................................... ..... 407 21.3.6 operation of lcd controller ........................................................................................... ............ 408 21.4 register set ............................................................................................................ ................ 413 21.4.1 hrtotalreg (0x0a00 0400) .............................................................................................. .... 414 21.4.2 hrvisibreg (0x0a00 0402) .............................................................................................. ...... 414 21.4.3 ldclkstreg (0x0a00 0404) .............................................................................................. .... 415 21.4.4 ldclkendreg (0x0a00 0406) ............................................................................................. .. 415 21.4.5 vrtotalreg (0x0a00 0408) .............................................................................................. .... 416 21.4.6 vrvisibreg (0x0a00 040a) .............................................................................................. ...... 416 21.4.7 fvstartreg (0x0a00 040c) .............................................................................................. ... 417 21.4.8 fvendreg (0x0a00 040e) ................................................................................................ ...... 417 21.4.9 lcdctrlreg (0x0a00 0410) .............................................................................................. .... 418 21.4.10 lcdinrqreg (0x0a00 0412) ............................................................................................. ... 419 21.4.11 lcdcfgreg0 (0x0a00 0414) ............................................................................................. ... 420 21.4.12 lcdcfgreg1 (0x0a00 0416) ............................................................................................. ... 421 user?s manual u14272ej3v0um 23 21.4.13 fbstadreg1 (0x0a00 0418) ............................................................................................. ... 422 21.4.14 fbstadreg2 (0x0a00 041a) ............................................................................................. ... 422 21.4.15 fbendadreg1 (0x0a00 0420) ............................................................................................ . 423 21.4.16 fbendadreg2 (0x0a00 0422) ............................................................................................ . 423 21.4.17 fhstartreg (0x0a00 0424) ............................................................................................. ... 424 21.4.18 fhendreg (0x0a00 0426) ............................................................................................... ..... 424 21.4.19 pwrconreg1 (0x0a00 0430) ............................................................................................. . 425 21.4.20 pwrconreg2 (0x0a00 0432) ............................................................................................. . 426 21.4.21 lcdimskreg (0x0a00 0434) ............................................................................................. ... 427 21.4.22 cpindctreg (0x0a00 047e) ............................................................................................. ... 428 21.4.23 cpaldatreg (0x0a0 0480) .............................................................................................. .... 429 chapter 22 pll passive components ................................................................................... 430 chapter 23 coprocessor 0 hazards ................................................................................... 431 appendix a restrictions on v r 4181 ....................................................................................... 436 a.1 rstsw# during haltimer operation .................................................................................. 436 a.2 rstsw# in hibernate mode ................................................................................................. .. 437 appendix b index ........................................................................................................... .................. 439 user?s manual u14272ej3v0um 24 list of figures (1/3) fig. no. title page 1-1. internal block diagram .................................................................................................... ............................ 30 1-2. v r 4110 cpu core internal block diagram .......................................................................................... ....... 35 1-3. cpu registers ............................................................................................................. ............................... 37 1-4. cpu instruction formats (32-bit length instruction) ....................................................................... ........... 38 1-5. cpu instruction formats (16-bit length instruction) ....................................................................... ........... 39 1-6. byte address in little-endian byte order .................................................................................. .................. 41 1-7. unaligned word accessing (little endian) ................................................................................. ................. 42 1-8. external circuits of clock oscillator ..................................................................................... ....................... 48 1-9. incorrect connection circuits of resonator ................................................................................ ................ 49 3-1. index register ............................................................................................................ ................................. 69 3-2. random register ........................................................................................................... ............................. 69 3-3. entrylo0 and entrylo1 registers ........................................................................................... .................... 70 3-4. context register .......................................................................................................... ............................... 71 3-5. pagemask register ......................................................................................................... ............................ 72 3-6. positions indicated by the wired register ................................................................................. ................. 73 3-7. wired register ............................................................................................................ ................................ 73 3-8. badvaddr register ......................................................................................................... ............................ 74 3-9. count register ............................................................................................................ ................................ 74 3-10. entryhi register ......................................................................................................... ................................. 75 3-11. compare register ......................................................................................................... .............................. 76 3-12. status register .......................................................................................................... .................................. 76 3-13. status register diagnostic status field .................................................................................. .................... 77 3-14. cause register ........................................................................................................... ................................ 79 3-15. epc register (when mips16 isa is disabled) ............................................................................... ........... 81 3-16. epc register (when mips16 isa is enabled) ................................................................................ ........... 82 3-17. prid register ............................................................................................................ .................................. 82 3-18. config register .......................................................................................................... ................................. 83 3-19. lladdr register .......................................................................................................... ................................ 84 3-20. watchlo register ......................................................................................................... ............................... 85 3-21. watchhi register ......................................................................................................... ............................... 85 3-22. xcontext register ........................................................................................................ ............................... 86 3-23. parity error register .................................................................................................... ................................ 87 3-24. cache error register ..................................................................................................... ............................. 87 3-25. taglo register ........................................................................................................... ................................. 88 3-26. taghi register ........................................................................................................... ................................. 88 3-27. errorepc register (when mips16 isa is disabled) .......................................................................... ........ 90 3-28. errorepc register (when mips16 isa is enabled) ........................................................................... ........ 90 4-1. v r 4181 physical address space ................................................................................................... ............. 92 user?s manual u14272ej3v0um 25 list of figures (2/3) fig. no. title page 5-1. rtc reset ................................................................................................................. ................................. 97 5-2. rstsw reset ............................................................................................................... .............................. 98 5-3. deadman?s switch reset .................................................................................................... ........................ 99 5-4. software shutdown ......................................................................................................... ............................ 100 5-5. haltimer shutdown ......................................................................................................... .......................... 101 5-6. v r 4181 activation sequence (when activation is ok) .............................................................................. . 102 5-7. v r 4181 activation sequence (when activation is ng) .............................................................................. 103 5-8. cold reset ................................................................................................................ .................................. 104 5-9. soft reset ................................................................................................................ ................................... 105 6-1. v r 4181 internal bus structure ................................................................................................... ................. 108 6-2. rom read cycle and access parameters ...................................................................................... ........... 114 6-3. ordinary rom read cycle (wroma(3:0) = 0101) ............................................................................... ..... 125 6-4. pagerom read cycle (wroma(3:0) = 0011, wprom(2:0) = 001) ......................................................... 126 6-5. flash memory read cycle (rtype(1:0) = 01, wroma(3:0) = 0101) .......................................................... 127 6-6. flash memory write cycle (rtype(1:0) = 01, wroma(3:0) = 0100) .......................................................... 127 6-7. external edo dram configuration ........................................................................................... ................. 128 6-8. sdram configuration ....................................................................................................... .......................... 130 8-1. sck and si/so relationship ................................................................................................ ...................... 157 9-1. outline of interrupt control .............................................................................................. ............................ 172 10-1. transition of v r 4181 power mode .............................................................................................................. 1 89 10-2. edo dram signals on rstsw reset (sdram bit = 0) .......................................................................... . 192 10-3. activation via power switch interrupt request (battinh = h) .............................................................. .... 195 10-4. activation via power switch interrupt request (battinh = l) .............................................................. .... 195 10-5. activation via compactflash interrupt request (battinh = h) .............................................................. .. 196 10-6. activation via compactflash interrupt request (battinh = l) .............................................................. ... 196 10-7. activation via gpio activation interrupt request (battinh = h) ........................................................... ... 197 10-8. activation via gpio activation interrupt request (battinh = l) ........................................................... .... 197 10-9. activation via dcd interrupt request (battinh = h) ....................................................................... ......... 199 10-10. activation via dcd interrupt request (battinh = l) ...................................................................... .......... 199 10-11. activation via elapsedtime interrupt request (battinh = h) .............................................................. ..... 200 10-12. activation via elapsedtime interrupt request (battinh = l) .............................................................. ..... 200 13-1. gpio(15:0) interrupt request detecting logic ............................................................................. .............. 243 user?s manual u14272ej3v0um 26 list of figures (3/3) fig. no. title page 14-1. piu peripheral block diagram ............................................................................................. ....................... 276 14-2. coordinate detection equivalent circuits ................................................................................. ................... 277 14-3. internal block diagram of piu ............................................................................................ ......................... 277 14-4. scan sequencer state transition diagram .................................................................................. ............... 278 14-5. interval times and states ................................................................................................ ........................... 286 14-6. touch/release detection timing ........................................................................................... ..................... 298 14-7. a/d port scan timing ..................................................................................................... ............................. 298 15-1. speaker output and audioout pin .......................................................................................... ................ 315 15-2. audioin pin and microphone operation ..................................................................................... ............... 316 16-1. scanout signal output timing ............................................................................................. ................... 319 17-1. compactflash interrupt logic ............................................................................................. ........................ 333 17-2. mapping of compactflash memory space ..................................................................................... ............ 350 17-3. mapping of compactflash i/o space ........................................................................................ ................. 351 19-1. siu1 block diagram ....................................................................................................... ............................. 360 20-1. siu2 block diagram ....................................................................................................... ............................. 379 21-1. lcd controller block diagram ............................................................................................. ....................... 401 21-2. view rectangle and horizontal/vertical blank ............................................................................. ............... 402 21-3. position of load clock (loclk) ........................................................................................... ...................... 403 21-4. position of frame clock (flm) ............................................................................................ ....................... 404 21-5. monochrome panel ......................................................................................................... ............................ 408 21-6. color panel in 8-bit data bus ............................................................................................ ......................... 409 21-7. load clock (loclk) ....................................................................................................... ............................ 410 21-8. frame clock (flm) ........................................................................................................ ............................. 410 21-9. lcd timing parameters .................................................................................................... .......................... 411 21-10. flm period .............................................................................................................. .................................... 411 22-1. example of connection of pll passive components .......................................................................... ....... 430 a-1. mask circuit for rstsw# signal ............................................................................................ .................... 436 a-2. release of self-refresh mode by rstsw# signal (edo dram) .............................................................. 437 a-3. release of self-refresh mode by rstsw# signal (sdram) .................................................................... 4 38 user?s manual u14272ej3v0um 27 list of tables (1/2) table no. title page 1-1. supported pclock and tclock frequencies ................................................................................... ............ 31 1-2. devices supported by system bus ........................................................................................... .................. 31 1-3. gpio(31:0) pin functions .................................................................................................. ......................... 33 1-4. lcd panel resolutions (in pixels, typ.) ................................................................................... ................. 34 1-5. functions of lcd interface pins when lcd controller is disabled ........................................................... .34 1-6. system control coprocessor (cp0) register definitions ..................................................................... ...... 43 1-7. list of instructions supported by v r series processors ............................................................................. 46 3-1. cp0 registers ............................................................................................................. ................................ 68 3-2. cache algorithm ........................................................................................................... .............................. 71 3-3. mask values and page sizes ................................................................................................ ..................... 72 3-4. cause register exception code field ....................................................................................... ................. 80 4-1. v r 4181 physical address space ................................................................................................... ............. 93 4-2. rom address map ........................................................................................................... .......................... 93 4-3. internal i/o space 1 ...................................................................................................... .............................. 94 4-4. internal i/o space 2 ...................................................................................................... .............................. 94 4-5. mba bus i/o space ......................................................................................................... ........................... 95 4-6. dram address map .......................................................................................................... ......................... 95 6-1. bus control registers ..................................................................................................... ............................ 110 6-2. v r 4181 edo dram capacity ........................................................................................................ ............. 129 6-3. memory controller registers ............................................................................................... ....................... 131 6-4. isa bridge registers ...................................................................................................... ............................. 137 7-1. dcu registers ............................................................................................................. ............................... 144 8-1. csi registers ............................................................................................................. ................................. 160 9-1. icu registers ............................................................................................................. ................................. 173 10-1. overview of power modes .................................................................................................. ........................ 190 10-2. operations during reset .................................................................................................. .......................... 191 10-3. operations during shutdown ............................................................................................... ....................... 193 10-4. pmu registers ............................................................................................................ ................................ 208 11-1. rtc registers ............................................................................................................ ................................ 216 12-1. dsu registers ............................................................................................................ ................................ 230 13-1. alternate functions of gpio(15:0) pins ................................................................................... ................... 236 13-2. alternate functions of gpio(31:16) pins .................................................................................. .................. 237 13-3. csi interface signals .................................................................................................... .............................. 238 13-4. serial interface channel 1 (siu1) signals ................................................................................ .................. 239 user?s manual u14272ej3v0um 28 list of tables (2/2) table no. title page 13-5. serial interface channel 1 (siu1) loopback control ....................................................................... ........... 239 13-6. serial interface channel 2 (siu2) signals ................................................................................ .................. 240 13-7. serial interface channel 2 (siu2) loopback control ....................................................................... ........... 240 13-8. stn color lcd interface signals .......................................................................................... ..................... 241 13-9. external lcd controller interface signals ................................................................................ .................. 241 13-10. programmable chip select signals ........................................................................................ .................... 242 13-11. giu registers ........................................................................................................... ................................... 244 14-1. piu registers ............................................................................................................ .................................. 280 14-2. piu interrupt registers .................................................................................................. .............................. 280 14-3. piucntreg bit manipulation and states .................................................................................... .............. 283 14-4. piuascnreg bit manipulation and states ................................................................................... ............. 290 14-5. detected data and page buffers ........................................................................................... ..................... 293 14-6. a/d ports and data buffers ............................................................................................... .......................... 294 14-7. mask clear during scan sequencer operation ............................................................................... ........... 295 15-1. aiu registers ............................................................................................................ .................................. 302 15-2. aiu interrupt registers .................................................................................................. .............................. 302 16-1. settings of keyboard scan mode ........................................................................................... ..................... 318 16-2. kiu registers ............................................................................................................ .................................. 321 16-3. kiu interrupt registers .................................................................................................. .............................. 321 17-1. ecu control registers .................................................................................................... ............................ 328 17-2. ecu registers ............................................................................................................ ................................ 329 18-1. led registers ............................................................................................................ ................................. 353 19-1. siu1 registers ........................................................................................................... ................................. 361 19-2. correspondence between baud rates and divisors ........................................................................... ....... 365 19-3. interrupt function ....................................................................................................... ................................. 367 20-1. siu2 registers ........................................................................................................... ................................. 380 20-2. correspondence between baud rates and divisors ........................................................................... ....... 384 20-3. interrupt function ....................................................................................................... ................................. 386 21-1. lcd panel resolutions (in pixels, typ.) .................................................................................. .................. 399 21-2. redefining lcd interface pins when lcd controller is disabled ............................................................ .. 400 21-3. lcd controller parameters ................................................................................................ ......................... 412 21-4. lcd controller registers ................................................................................................. ........................... 413 23-1. coprocessor 0 hazards .................................................................................................... .......................... 432 23-2. calculation example of cp0 hazard and number of instructions inserted ................................................. 435 user?s manual u14272ej3v0um 29 chapter 1 introduction this chapter describes the outline of the v r 4181 ( pd30181), which is a 64-/32-bit microprocessor. 1.1 features the v r 4181, which is a high-performance 64-/32-bit microprocessor employing the risc (reduced instruction set computer) architecture developed by mips tm , is one of the v r -series microprocessor products manufactured by nec electronics. the v r 4181 contains the v r 4110 tm cpu core of ultra-low-power consumption with cache memory, high-speed product-sum operation unit, and memory management unit. it also has interface units for peripheral circuits such as lcd controller, compactflash controller, dma controller, keyboard interface, serial interface, irda interface, touch panel interface, real-time clock, a/d converter and d/a converter required for the battery-driven portable information equipment. the features of the v r 4181 are described below. ? employs 0.25 m process ? 64-bit risc v r 4110 cpu core with pipeline clock up to 66 mhz (operation in 32-bit mode is available) ? optimized 5-stage pipeline ? on-chip instruction and data caches with 4 kb each in size ? write-back cache for reducing store operation that use the system bus ? 32-bit physical address space and 40-bit virtual address space, and 32 double-entry tlb ? instruction set: mips iii (with the fpu, ll and sc instructions left out) and mips16 ? supports madd16 and dmadd16 instructions for executing a multiply-and-accumulate operation of 16-bit data x 16-bit data + 64-bit data within one clock cycle ? effective power management features, which include four operating modes, fullspeed, standby, suspend and hibernate mode ? on-chip pll and clock generator ? dram interface supporting 16-bit width sdram and edo dram ? ordinary rom/pagerom/flash memory interface ? uma based lcd controller ? 4-channel dma controller ? rtc unit including 3-channel timers and counters ? two uart-compatible serial interfaces and one clocked serial interface ? irda (sir) interface ? keyboard scan interface supporting 8 x 8 key matrix ? x-y auto-scan touch panel interface ? compactflash interface compatible with exca ? a/d and d/a converters ? includes isa-subset bus ? supply voltage: 2.5 v for cpu core, 3.3 v for i/o ? package: 160-pin lqfp chapter 1 introduction user?s manual u14272ej3v0um 30 1.2 ordering information part number package maximum internal operating frequency pd30181gm-66-8ed 160-pin plastic lqfp (fine pitch) (24 24) 66 mhz 1.3 v r 4181 key features figure 1-1. internal block diagram lcd panel 32.768 khz 18.432 mhz edo dram/ sdram rom/ flash memory lcd controller clock generator v r 4110 cpu core mba tm host bridge isa bridge pmu piu siu1 siu2 ir module rs-232-c driver giu led led v r 4181 icu rtc speaker microphone touch panel battery monitor compactflash card bus control memory controller ecu dcu buf buf aiu d/a csi kiu a/d dsu keyboard (8 x 8) isa bus mba bus system bus (isa) chapter 1 introduction user ? s manual u14272ej3v0um 31 1.3.1 cpu core the v r 4181 integrates an nec electronics ? v r 4110 cpu core supporting both the mips iii and mips16 instruction sets. the v r 4181 supports the following pipeline clock (pclock) and internal bus clock (tclock) frequencies. the pclock is set by attaching pull-up or pull-down resistors to the clksel(2:0) pins. the frequency of the tclock, which is used in mba bus, is set by pmudivreg register in power management unit. table 1-1. supported pclock and tclock frequencies pclock frequency tclock frequency 65.4 mhz 65.4/32.7/21.8 mhz 62.0 mhz 62.0/31.0/20.7 mhz 49.1 mhz 49.1/24.6 mhz the v r 4110 core of the v r 4181 includes 4 kb of instruction cache and 4 kb of data cache. the v r 4110 core also supports the following power management modes: ? ? ? note ? note suspend mode is supported only when the internal lcd controller has been disabled or the lcd panel has been powered off. 1.3.2 bus interface the v r 4181 incorporates single bus architecture. all external memory and i/o devices are connected to the same 22-bit address bus and 16-bit data bus. these external address and data bus are together called the system bus. when the external bus operates at a very high speed, the dram data bus must be isolated from other low speed devices such as rom array. the v r 4181 provides two pins, sysen# and sysdir, to control the data buffers for this isolation. the v r 4181 supports the following types of devices connected to the system bus. table 1-2. devices supported by system bus device data width rom, flash memory 16 bits only dram 16 bits only compactflash 8 or 16 bits external i/o 8 or 16 bits external memory 8 or 16 bits six of the external bus interface signals, iord#, iowr#, iordy, iocs16#, memcs16# and reset#, can be individually defined as general-purpose i/o pins or lcd interface pin if they are not needed by external system components. chapter 1 introduction user ? s manual u14272ej3v0um 32 1.3.3 memory interface the v r 4181 provides control for both rom/flash memory and dram. up to four 16-bit rom/flash memory banks may be supported utilizing either 32-mbit or 64-mbit single cycle or page mode devices. bank mixing is not supported for rom/flash memory. when a system implements less than the maximum 4 banks of rom/flash memory, unused rom chip select pins can be defined as general-purpose i/o pins. the v r 4181 also supports up to 2 banks of 1m x 16 or 4m x 16 edo-type dram or sdram at bus frequencies of up to 66 mhz. when both banks are edo-type dram, bank mixing is supported. 1.3.4 dma controller (dcu) the v r 4181 provides a 4-channel dma controller to support internal dma transfers. the 4 channels are allocated as follows: ? ? ? 1.3.5 interrupt controller (icu) the v r 4181 provides an interrupt controller which combines all interrupt request sources into one of the v r 4110 core interrupt inputs - nmi and int(2:0). the interrupt controller also provides interrupt request status reporting. 1.3.6 real-time clock the v r 4181 includes a real-time clock (rtc), which allows time keeping based on the 32.768 khz clock as a source. the rtc operates as long as the v r 4181 remains powered. 1.3.7 audio output (d/a converter) the v r 4181 provides a 1-channel 10-bit d/a converter for generating audio output. 1.3.8 touch panel interface and audio input (a/d converter) the v r 4181 provides an 8-channel 10-bit a/d converter for interfacing to a touch panel, an external microphone, and other types of analog input. 1.3.9 compactflash interface (ecu) the v r 4181 provides an exca-compatible bus controller supporting a single compactflash slot. this interface is shared with the keyboard interface logic and must be disabled when an 8 x 8 key matrix is connected to the v r 4181. 1.3.10 serial interface channel 1 (siu1) the v r 4181 provides a 16550 uart for implementing an rs-232-c type serial interface. when the serial interface is not needed, each of the 7 serial interface pins can be individually redefined as general-purpose i/o pins. 1.3.11 serial interface channel 2 (siu2) the serial interface channel 2 is also based on a 16550 uart but only reserves 2 pins for the interface. the serial interface channel 2 can be configured in one of the following modes: ? ? ? chapter 1 introduction user ? s manual u14272ej3v0um 33 1.3.12 clocked serial interface (csi) the v r 4181 provides a clocked serial interface (csi) which has an option to be configured as general-purpose i/o pins. this interface supports slave mode operation only. the clocked serial interface requires allocation of 4 signals; si, so, sck, and frm. the clock source for this interface is input on the pin assigned to sck. 1.3.13 keyboard interface (kiu) the v r 4181 provides support for an 8 x 8 key matrix. this keyboard interface can only be supported when the compactflash interface is disabled and reconfigured to provide the scanin(7:0) inputs and the scanout(7:0) outputs. 1.3.14 general-purpose i/o the v r 4181 provides total 32 bits of general-purpose i/o. sixteen of these, gpio(31:16), are available through pins allocated to other functions as shown in the following table. the dcd1#/gpio29 is the only one of the 16 pins that can cause the system ? s waking up from a low power mode if enabled by software. the other pins have no functions other than those listed below. the remaining 16 bits of general-purpose i/o, gpio(15:0), are allocated to pins by default. each of these pins can be configured to support a particular interface such as csi, secondary serial interface (rs-232-c), programmable chip selects, or color lcd control. otherwise, each of these pins can be also defined as one of the following: ? ? ? ? table 1-3. gpio(31:0) pin functions pin designation alternate function pin designation alternate function gpio0 si gpio16 iord# gpio1 so gpio17 iowr# gpio2 sck gpio18 iordy gpio3 pcs0# gpio19 iocs16# gpio4 ? note m/ube# gpio5 dcd2# gpio21 r eset# gpio6 rts2# gpio22 romcs0# gpio7 dtr2# gpio23 romcs1# gpio8 dsr2# gpio24 romcs2# gpio9 cts2# gpio25 rxd1 gpio10 frm/sysclk gpio26 txd1 gpio11 pcs1# gpio27 rts1# gpio12 fpd4 gpio28 cts1# gpio13 fpd5 gpio29 dcd1# gpio14 fpd6/cd1# gpio30 dtr1# gpio15 fpd7/cd2# gpio31 dsr1# note this signal supports input only. chapter 1 introduction user ? s manual u14272ej3v0um 34 1.3.15 programmable chip selects the v r 4181 provides support for 2 programmable chip selects (pcs) which are also available as general-purpose i/o pins. each pcs can decode either i/o or memory accesses and can optionally be qualified to read, write, or both read and write. 1.3.16 lcd interface the lcd controller of the v r 4181 is unified memory architecture (uma) based in which the frame buffer is part of system dram. the lcd controller supports monochrome stn lcd panels having 4-bit data bus interfaces and color stn lcd panels having 8-bit data bus interface. when interfacing to a color lcd panel, general-purpose i/o pins must be allocated to provide the upper nibble of the 8-bit lcd data bus. in monochrome mode, the lcd controller supports 1-bpp mode (mono), 2-bpp mode (4 gray levels) and 4-bpp mode (16 gray levels). in color mode, it supports 4-bpp mode (16 colors) and 8-bpp mode (256 colors). the lcd controller includes a 256-entry x 18-bit color pallet. in 8-bpp color modes, the pallet is used to select 256 colors out of possible 262,144 colors. the lcd controller supports lcd panels of up to 320 x 320 pixels. typical lcd panel horizontal/vertical resolutions are as follows. table 1-4. lcd panel resolutions (in pixels, typ.) horizontal resolution vertical resolution 320 320 320 240 320 160 240 320 240 240 240 160 160 320 160 240 160 160 the lcd controller also provides power-on and power-down sequence control for the lcd panel via the vplcd and vpbias pins. power sequencing is provided to prevent latch-up damage to the panel. the lcd controller can be disabled to allow connection of an external lcdc with integrated frame buffer ram such as nec electronics ? table 1-5. functions of lcd interface pins when lcd controller is disabled redefined function default function lcdcs# shclk memcs16# loclk vpgpio1 vplcd vpgpio0 vpbias chapter 1 introduction user ? s manual u14272ej3v0um 35 1.3.17 wake-up events the v r 4181 supports 4 power management modes: fullspeed, standby, suspend, and hibernate. of these modes, hibernate is the lowest power mode and results in the powering off of all system components including the 2.5 v logic in the v r 4181. the v r 4181 3.3 v logic, which includes rtc, pmu, and non-volatile registers, remain powered during the hibernate mode, as does the system dram. software can configure the v r 4181 waking up from the hibernate mode and returning to fullspeed mode due to any one of the following events: ? ? ? ? ? remark different from the v r 4111 tm or the v r 4121 tm , the v r 4181 will wake up after rtc reset without these wake-up events. 1.4 v r 4110 cpu core figure 1-2 shows the internal block diagram of the v r 4110 cpu core. in addition to the conventional high-performance integer operation units, this cpu core has the full-associative format translation lookaside buffer (tlb), which has 32 entries that provide mapping to 2-page pairs (odd and even) for one entry. moreover, it also includes instruction cache, data cache, and bus interface. figure 1-2. v r 4110 cpu core internal block diagram tlb virtual address bus internal data bus bus interface data cache (4 kb) instruction cache (4 kb) clock generator cp0 cpu control(o) control(i) address/data(o) address/data(i) internal clock chapter 1 introduction user ? s manual u14272ej3v0um 36 (1) cpu the cpu has hardware resources to process an integer instruction. they are the 64-bit register file, 64-bit integer data path, and multiply-and-accumulate operation unit. (2) coprocessor 0 (cp0) the cp0 incorporates a memory management unit (mmu) and exception handling function. mmu checks whether there is an access between different memory segments (user, supervisor, and kernel) by executing address translation. the translation lookaside buffer (tlb) translates virtual addresses to physical addresses. (3) instruction cache the instruction cache employs direct mapping, virtual index, and physical tag. its capacity is 4 kb. (4) data cache the data cache employs direct mapping, virtual index, physical tag, and writeback. its capacity is 4 kb. (5) cpu bus interface the cpu bus interface controls data transmission/reception between the v r 4110 core and the mba host bridge. this interface consists of two 32-bit multiplexed address/data buses (one is for input, and another is for output), clock signal, and control signals such as interrupt requests. (6) clock generator the following clock inputs are oscillated and supplied to internal units. ? ? ? s reference operating clock crystal resonator input oscillated via an internal oscillator, and then multiplied by phase-locked loop (pll) to generate a pipeline clock (pclock). the internal bus clock (tclock) is generated from pclock and supplied to peripheral units. chapter 1 introduction user ? s manual u14272ej3v0um 37 1.4.1 cpu registers the v r 4110 core has thirty-two 64-bit general-purpose registers (gprs). in addition, the processor provides the following special registers: ? ? ? ? ? v r 4100 series architecture user?s manual . the v r 4181 has no program status word (psw) register as such; this is covered by the status and cause registers incorporated within the cp0 (see 1.4.4 cp0 registers ). figure 1-3 shows the cpu registers. figure 1-3. cpu registers 0 31 32 63 hi 0 31 32 63 lo 0 pc 31 general-purpose registers multiply/divide registers program counter 0 32 31 63 32 63 r2 r1 r0 = 0 r31 = linkaddress r30 r29 chapter 1 introduction user ? s manual u14272ej3v0um 38 1.4.2 cpu instruction set overview there are two types of cpu instructions: 32-bit length instructions (mips iii) and 16-bit length instructions (mips16). use of the mips16 instructions is enabled or disabled by setting mips16en pin during a reset. for details about instruction formats and their fields in each instruction set and operation of each instruction, refer to v r 4100 series architecture user?s manual . (1) mips iii instructions all the cpu instructions are 32-bit length when executing mips iii instructions, and they are classified into three instruction formats as shown in figure 1-4: immediate (i type), jump (j type), and register (r type). figure 1-4. cpu instruction formats (32-bit length instruction) 31 26 25 21 20 16 15 0 op rs rt immediate i - type (immediate) 31 26 25 0 op target j - type (jump) 31 26 25 21 20 16 15 0 op rs rt sa r - type (register) 11 10 6 5 rd funct the instruction set can be further divided into the following five groupings: (a) load and store instructions move data between the memory and the general-purpose registers. they are all immediate (i-type) instructions, since the only addressing mode supported is base register plus 16-bit, signed immediate offset. (b) computational instructions perform arithmetic, logical, shift, and multiply and divide operations on values in registers. they include r-type (in which both the operands and the result are stored in registers) and i-type (in which one operand is a 16-bit signed immediate value) formats. (c) jump and branch instructions change the control flow of a program. jumps are made either to an absolute address formed by combining a 26-bit target address with the higher bits of the program counter (j-type format) or register-specified address (r-type format). the format of the branch instructions is i type. branches have 16-bit offsets relative to the program counter. jal instructions save their return address in register 31. (d) system control coprocessor (cp0) instructions perform operations on cp0 registers to control the memory- management and exception-handling facilities of the processor. (e) special instructions perform system calls and breakpoint exceptions, or cause a branch to the general exception-handling vector based upon the result of a comparison. these instructions occur in both r-type and i-type formats. chapter 1 introduction user ? s manual u14272ej3v0um 39 (2) mips16 instructions all the cpu instructions except for jal and jalx are 16-bit length when executing mips16 instructions, and they are classified into thirteen instruction formats as shown in figure 1-5. figure 1-5. cpu instruction formats (16-bit length instruction) op i-type ri-type rr-type rri-type rrr-type rri-a-type shift-type i8-type i8_movr32-type i8_mov32r-type i64-type ri64-type jal/jalx-type immediate 0 10 11 op immediate 0 11 15 15 rx 10 8 7 op funct 0 11 15 rx 10 8 7 ry 54 rri immediate 0 11 15 rx 10 8 7 ry 54 rrr f 0 11 15 rx 10 8 7 ry 54 5 4 rz 21 rri-a f 0 11 15 rx 10 8 7 ry immediate 3 shift f 0 11 15 rx 10 8 7 ry shamt 21 i8 immediate 0 11 15 funct 10 8 7 i8 r32(4:0) 0 11 15 funct 10 8 7 ry i8 r32(2:0) funct rz 0 11 15 10 8 7 3 2 i64 immediate 0 11 15 funct 10 8 7 i64 immediate 0 11 15 funct 10 8 7 ry 54 jal immediate(15:0) 0 31 immediate(25:21) x immediate(20:16) 11 10 9 5 4 54 54 54 r32(4:3) 16 15 chapter 1 introduction user ? s manual u14272ej3v0um 40 the instruction set can be further divided into the following four groupings: (a) load and store instructions move data between memory and general-purpose registers. they include rri, ri, i8, and ri64 types. (b) computational instructions perform arithmetic, logical, shift, and multiply and divide operations on values in registers. they include ri, rria, i8, ri64, i64, rr, rrr, i8_movr32, and i8_mov32r types. (c) jump and branch instructions change the control flow of a program. they include jal/jalx, rr, ri, i8, and i types. (d) special instructions are break and extend instructions. the break instruction transfers control to an exception handler. the extend instruction extends the immediate field of the next instruction. they are rr and i types. when extending the immediate field of the next instruction by using the extend instruction, one cycle is needed for executing the extend instruction, and another cycle is needed for executing the next instruction. 1.4.3 data formats and addressing the v r 4181 uses the following four data formats: ? ? ? ? chapter 1 introduction user ? s manual u14272ej3v0um 41 figure 1-6. byte address in little-endian byte order (a) word data 15 11 7 3 14 10 6 2 13 9 5 1 12 8 4 0 31 24 23 16 15 8 7 0 12 8 4 0 word address high-order address low-order address (b) doubleword data 23 15 7 22 14 6 21 13 5 20 12 4 16 8 0 doubleword address high-order address low-order address 19 11 3 18 10 2 17 9 1 16 8 0 63 0 32 31 16 15 8 7 word halfword byte remarks 1. the lowest byte is the lowest address. 2. the address of word data is specified by the lowest byte ? s address. chapter 1 introduction user ? s manual u14272ej3v0um 42 the cpu core uses the following byte boundaries for halfword, word, and doubleword accesses: ? ? ? ? ? figure 1-7. unaligned word accessing (little endian) 31 24 23 16 15 8 7 0 65 4 3 high-order address low-order address chapter 1 introduction user ? s manual u14272ej3v0um 43 1.4.4 cp0 registers the cp0 has thirty-two registers, each of which has its own register number. table 1-6 shows simple descriptions of each register. for the detailed descriptions of the registers, refer to chapter 3 cp0 registers . table 1-6. system control coprocessor (cp0) register definitions number register usage description 0 index memory management programmable pointer to tlb array 1 random memory management pseudo-random pointer to tlb array (read only) 2 entrylo0 memory management lower half of tlb entry for even vpn 3 entrylo1 memory management lower half of tlb entry for odd vpn 4 context exception processing pointer to kernel virtual pte in 32-bit mode 5 pagemask memory management page size specification 6 wired memory management number of wired tlb entries 7 ?? note1 memory management physical address for self diagnostics 18 watchlo exception processing memory reference trap address low bits 19 watchhi exception processing memory reference trap address high bits 20 xcontext exception processing pointer to kernel virtual pte in 64-bit mode 21 to 25 ?? note2 exception processing cache parity bits 27 cache error note2 exception processing index and status of cache error 28 taglo memory management lower half of cache tag 29 taghi memory management higher half of cache tag 30 errorepc exception processing error exception program counter 31 ?? notes1. this register is defined to maintain compatibility with the v r 4000 tm and v r 4400 tm . this register is meaningless during normal operations. 2. this register is defined to maintain compatibility with the v r 4100 tm . this register is not used in the v r 4181 hardware. chapter 1 introduction user ? s manual u14272ej3v0um 44 1.4.5 floating-point unit (fpu) the v r 4181 does not support the floating-point unit (fpu). coprocessor unusable exception will occur if any fpu instructions are executed. if necessary, fpu instructions should be emulated by software in an exception handler. 1.4.6 memory management unit the v r 4181 has a 32-bit physical addressing range of 4 gb. however, since it is rare for systems to implement a physical memory space as large as that memory space, the cpu provides a logical expansion of memory space by translating addresses composed in the large virtual address space into available physical memory addresses. the v r 4181 has three operating modes: user, supervisor, and kernel. the manner in which memory addresses are mapped depends on these operating modes. in addition, the v r 4181 supports the 32-bit and 64-bit addressing modes. the manner in which memory addresses are translated or mapped depends on these addressing modes. a detailed description of the physical address space is given in chapter 4 memory management system . for details about the virtual address space, refer to v r 4100 series architecture user?s manual . (1) translation lookaside buffer (tlb) virtual memory mapping is performed using the translation lookaside buffer (tlb). the tlb translates virtual addresses to physical addresses. it runs by a full-associative method and has 32 entries, each of which two successive pages are mapped. the tlb of the v r 4181 holds both instruction addresses and data addresses so that it is called as joint tlb (jtlb). the page size can be configured, on a per-entry basis, to map a page size of 1 kb to 256 kb, in power of four. a cp0 register stores the size of the page to be mapped, and that size is entered into the tlb when a new entry is written. thus, operating systems can provide special purpose maps; for example, a typical frame buffer can be memory-mapped using only one tlb entry. translating a virtual address to a physical address begins by comparing the virtual address from the processor with the physical addresses in the tlb. there is a match when the virtual page number (vpn) of the address is the same as the vpn field of an entry, and either the global (g) bit of the tlb entry is set, or the asid field of the virtual address is the same as the asid field of the tlb entry. this match is referred to as a tlb hit. if there is no match, a tlb miss exception is taken by the processor and software is allowed to refill the tlb from a page table of virtual/physical addresses in memory. 1.4.7 cache the v r 4181 chip incorporates instruction and data caches, which are independent of each other. this configuration enables high-performance pipeline operations. both caches have a 64-bit data bus, enabling a one- clock access. these buses can be accessed in parallel. the instruction cache of the v r 4181 has a storage capacity of 4 kb, while the data cache has a capacity of 4 kb. for details about caches, refer to v r 4100 series architecture user?s manual . 1.4.8 instruction pipeline the v r 4181 has a 5-stage instruction pipeline. under normal circumstances, one instruction is issued each cycle. for details, refer to v r 4100 series architecture user?s manual . chapter 1 introduction user ? s manual u14272ej3v0um 45 1.4.9 power modes the v r 4181 supports four power modes: fullspeed mode, standby mode, suspend mode, and hibernate mode. a detailed description of these power modes is also given in chapter 10 power management unit (pmu) . (1) fullspeed mode this is the normal operation mode. the v r 4181 ? s default status sets operation under fullspeed mode. after a reset, the v r 4181 returns to fullspeed mode. (2) standby mode when a standby instruction has been executed, the processor can be set to standby mode. during standby mode, the pipeline clock (pclock) in the cpu core is held at high level. the peripheral units all operate as they do during fullspeed mode. this means that dma operations are enabled during standby mode. during standby mode, the processor returns to fullspeed mode if any interrupt request occurs. (3) suspend mode when the suspend instruction has been executed, the processor can be set to suspend mode. during suspend mode, the pipeline clock (pclock) in the cpu core is held at high level. the v r 4181 also stops supplying tclock and pclk to peripheral units. while in this mode, the register and cache contents are retained. contents of dram can also be retained by putting dram into self-refresh mode. during suspend mode, the processor returns to fullspeed mode if any of power-on factors or some of interrupt requests occurs. (4) hibernate mode when the hibernate instruction has been executed, the processor can be set to hibernate mode. during hibernate mode, clocks other than the rtc clock (32.768 khz) are held at high level and the pll stops. while in this mode, contents of the registers and caches are not retained. contents of dram can be retained by putting dram into self-refresh mode. power consumption during hibernate mode is about 0 w if power to 2.5 v power supply is not applied (it does not go completely to 0 w due to the existence of a 32.768 khz oscillator or on-chip peripheral circuits that operate at 32.768 khz). during hibernate mode, the processor returns to fullspeed mode if any of power-on factors or some of interrupt requests occurs. chapter 1 introduction user ? s manual u14272ej3v0um 46 1.4.10 code compatibility the v r 4110 core is designed in consideration of the program compatibility to other v r -series processors. however since it has some differences from other processors on their architecture, it cannot necessarily execute all programs that can be executed in other v r -series processors, and also other v r -series processors cannot necessarily execute all programs that can be executed in the v r 4110 core. matters that should be paid attention to when porting programs between the v r 4110 core and other v r -series processors are listed below. ? ? ? ? ? ? v r 4100 series architecture user?s manual , and user ? s manuals of each product other than the v r 4100 series. instructions supported by each of the v r series processors are listed below. table 1-7. list of instructions supported by v r series processors products supported instructions v r 4181 v r 4111 v r 4121 v r 4122 tm v r 4300 tm v r 4305 tm v r 4310 tm v r 5000a tm v r 5432 tm v r 10000 tm v r 12000 tm mips i aaaaaa mips ii aaaaaa mips iii aaaaaa ll bit manipulation n/an/aaaaa mips iv n/a n/a n/a a a a mips16 a a n/a n/a n/a n/a multiply-add a (16 bits) a (32 bits) n/a n/a a (32 bits) n/a floating-point operation n/a n/a aaaa power mode transition a a n/a a a n/a chapter 1 introduction user ? s manual u14272ej3v0um 47 1.5 clock interface the v r 4181 has the following eight clocks. ? ? ? ? ? s count register are incremented synchronously with this clock. ? ? ? ? chapter 1 introduction user ? s manual u14272ej3v0um 48 figure 1-8 shows the external circuits of the clock oscillator. figure 1-8. external circuits of clock oscillator (a) crystal oscillation (b) external clock v r 4181 open external clock gnd_osc note 1 note 2 note 1 note 2 v r 4181 notes 1. clkx1, rtcx1 2. clkx2, rtcx2 cautions 1. when using the clock oscillator, wire as follows in the area enclosed by the broken line in the above figures to avoid an adverse effect from wiring capacitance. ? ? ? ? chapter 1 introduction user ? s manual u14272ej3v0um 49 figure 1-9. incorrect connection circuits of resonator (a) connection circuit wiring is too long. note 2 note 1 note 2 note 1 (b) there is another signal line crossing. (c) a high fluctuating current flows near a signal line. large current (d) a current flows over the ground line of the oscillator (the potentials of points a, b, and c change). abc v dd (e) a signal is fetched. note 2 note 1 note 2 note 1 note 1 note 2 notes 1. clkx2, rtcx2 2. clkx1, rtcx1 3. gnd_osc note 3 note 3 note 3 note 3 note 3 user?s manual u14272ej3v0um 50 chapter 2 pin functions 2.1 pin configuration ? 160-pin plastic lqfp (fine pitch) (24 24) fpd0 fpd1 fpd2 fpd3 gpio12/fpd4 gpio13/fpd5 gpio14/fpd6/cd1# gpio15/fpd7/cd2# ube#/gpio20/m iowr#/gpio17 iord#/gpio16 flm/mips16en vdd_logic gnd_logic loclk/memcs16# shclk/lcdcs# vpbias/vpgpio0 vplcd/vpgpio1 vdd_io gnd_io gpio0/si gpio1/so gpio2/sck gpio3/pcs0# gpio4 gpio5/dcd2# gnd_logic gpio6/rts2# gpio7/dtr2# gpio8/dsr2# gpio9/cts2# gpio10/frm/sysclk gpio11/pcs1# irdout/txd2 irdin/rxd2 rxd1/gpio25 txd1/gpio26/clksel0 rts1#/gpio27/clksel1 cts1#/gpio28 dcd1#/gpio29 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 data5 data6 data7 data8 data9 data10 data11 data12 data13 data14 data15 gnd_io vdd_io sdclk add0 add1 add2 add3 add4 add5 gnd_logic vdd_logic add6 add7 add8 add9 add10 add11 gnd_io vdd_io add12 add13 add14 add15 add16 add17 add18 add19 add20 add21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 dtr1#/gpio30/clksel2 dsr1#/gpio31 power rstsw# rtcrst# poweron mpower battinh/battint# vdd_logic gnd_logic cf_aen#/scanin0 cf_dir/scanin1 cf_den#/scanin2 cf_vccen#/scanin3 cf_iois16#/scanin4 cf_wait#/scanin5 cf_reset/scanin6 cf_reg#/scanin7 vdd_io gnd_io cf_busy#/scanout0 cf_ce1#/scanout1 cf_ce2#/scanout2 cf_stschg#/scanout3 cf_ior#/scanout4 cf_iow#/scanout5 cf_oe#/scanout6 cf_we#/scanout7 ledout gnd_io gnd_io vdd_pll gnd_pll vdd_osc clkx1 clkx2 rtcx2 rtcx1 gnd_osc gnd_io gnd_ad gnd_tp tpx0 tpx1 tpy0 tpy1 vdd_tp adin0 adin1 adin2 audioin vdd_ad audioout iordy/gpio18 iocs16#/gpio19 reset#/gpio21 romcs3# romcs2#/gpio24 romcs1#/gpio23 romcs0#/gpio22 sysen# sysdir memwr# memrd# gnd_logic vdd_logic ldqm/lcas# udqm/ucas# sdras# cas# ras0#/sdcs0# gnd_io vdd_io ras1#/sdcs1# clken data0 data1 data2 data3 data4 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 remark # indicates active low. chapter 2 pin functions user ? s manual u14272ej3v0um 51 pin identification add(21:0) : address bus adin(2:0) : analog data input audioin : audio input audioout : audio output battinh : battery inhibit battint# : battery interrupt cas# : column address strobe cd1#, cd2# : card detect for compactflash cf_aen# : address enable for compactflash buffer cf_busy# : ready/busy/interrupt request for compactflash cf_ce(2:1)# : card enable for compactflash cf_den# : data enable for compactflash buffer cf_dir : data direction for compactflash buffer cf_iois16# : i/o is 16 bits for compactflash cf_ior# : i/o read strobe for compactflash cf_iow# : i/o write strobe for compactflash cf_oe# : output enable for compactflash cf_reg# : register memory access for compactflash cf_reset : reset for compactflash cf_stschg# : status change of compactflash cf_vccen# : v cc enable for compactflash cf_wait# : wait input for compactflash cf_we# : write enable for compactflash clken : clock enable for sdram clksel(2:0) : clock select clkx1, clkx2 : clock input cts1#, cts2# : clear to send data(15:0) : data bus dcd1#, dcd2# : data carrier detect dsr1#, dsr2# : data set ready dtr1#, dtr2# : data terminal ready flm : first line clock for lcd fpd(7:0) : screen data of lcd frm : clocked serial frame gnd_ad : ground for a/d and d/a converter gnd_io : ground for i/o gnd_logic : ground for logic gnd_osc : ground for oscillator gnd_pll : ground for pll gnd_tp : ground for touch panel gpio(31:0) : general purpose i/o iocs16# : i/o 16-bit bus sizing iord# : i/o read iordy : i/o ready iowr# : i/o write irdin : irda data input irdout : irda data output lcas# : lower column address strobe lcdcs# : chip select for lcd ldqm : lower byte enable for sdram ledout : led output loclk : load clock for lcd m : lcd modulation clock memcs16# : memory 16-bit bus sizing memrd# : memory read memwr# : memory write mips16en : mips16 enable mpower : main power pcs(1:0)# : programmable chip select power : power switch poweron : power on state ras(1:0)# : row address strobe for dram reset# : reset output romcs(3:0)# : chip select for rom rstsw# : reset switch rtcrst# : real-time clock reset rtcx1, rtcx2 : real-time clock input rts1#, rts2# : request to send rxd1, rxd2 : receive data scanin(7:0) : scan data input scanout(7:0) : scan data output sck : csi (clocked serial interface) clock sdclk : operation clock for sdram sdcs(1:0)# : chip select for sdram sdras# : row address strobe for sdram shclk : shift clock for lcd si : clocked serial data input so : clocked serial data output sysclk : system clock for system bus sysdir : system data direction sysen# : system data enable tpx(1:0) : touch panel data of x tpy(1:0) : touch panel data of y txd1, txd2 : transmit data ube# : upper byte enable for system bus ucas# : upper column address strobe for dram udqm : upper byte enable for sdram vdd_ad : power supply for a/d and d/a converter vdd_io : power supply for i/o vdd_logic : power supply for logic vdd_osc : power supply for oscillator vdd_pll : power supply for pll vdd_tp : power supply for touch panel vpbias : bias power control for lcd vpgpio(1:0) : general purpose output for lcd panel power control vplcd : logic power control for lcd remark # indicates active low. chapter 2 pin functions user ? s manual u14272ej3v0um 52 2.2 pin function description remark # indicates active low. 2.2.1 system bus interface signals (1/2) signal name i/o description of function add(21:0) note output address bus. used to specify address for the dram, rom, flash memory, or system bus (isa). data(15:0) i/o data bus. used to transmit and receive data between the v r 4181 and dram, rom, flash memory, or system bus. iord#/gpio16 i/o system bus i/o read signal output or general-purpose i/o. it is active when the v r 4181 accesses the system bus to r ead data from an i/o port when configured as iord#. iowr#/gpio17 i/o system bus i/o write signal output or general-purpose i/o. it is active when the v r 4181 accesses the system bus to write data to an i/o port when configured as iowr#. iordy/gpio18 i/o system bus i/o channel ready input or general-purpose i/o. set this signal as active when system bus controller is r eady to be accessed by the v r 4181 when configured as iordy. iocs16#/gpio19 i/o bus sizing request input for system bus i/o or general-purpose i/o. set this signal as active when system bus i/o accesses data in 16-bit width, if configured as iocs16#. ube#/gpio20/m i/o system bus upper byte enable output, general-purpose input, or lcd modulation output. during system bus accesses, this si gnal is active when the high-order byte is valid on the data bus. reset#/gpio21 i/o system bus reset output or general-purpose i/o. it is active when the v r 4181 resets the system bus controller w hen configured as reset#. note the v r 4181 utilizes different addressings depending on the types of the external accesses. during rom accesses, bits 22 to 1 of the internal address lines are output to the add(21:0) pins (the minimum transfer data width is a half word (1 word = 32 bits)). during accesses other than rom accesses, bits 21 to 0 of the internal address lines are output to the add(21:0) pins (the minimum transfer data width is 1 byte). chapter 2 pin functions user ? s manual u14272ej3v0um 53 (2/2) signal name i/o description of function sysdir note output data bus isolation buffer direction control. this signal is valid only when rom, isa, or compactflash accesses are enabled. this becomes low level during rom, isa, or compactflash read cycle, or becomes high level during rom, isa, or compactflash write cycle. sysen# note output data bus isolation buffer enable. this signal is valid only when rom, isa, or compactflash accesses are enabled. this becomes active during rom or isa cycle. sdcs(1:0)#/ras(1:0)# output sdram chip select for bank 0 and bank 1 or edo dram row address strobes. cas# output sdram column address strobe. leave unconnected when using edo dram. sdras# output sdram row address strobe. leave unconnected when using edo dram. udqm/ucas# output sdram upper byte enable or edo dram upper byte column address strobe. ldqm/lcas# output sdram lower byte enable or edo dram lower byte column address strobe. sdclk output sdram operating clock. clken output sdram clock enable output (cke). romcs3# output rom chip select output for bank 3. romcs2#/gpio24 i/o rom chip select output for bank 2, or general-purpose i/o. romcs1#/gpio23 i/o rom chip select output for bank 1, or general-purpose i/o. romcs0#/gpio22 i/o rom chip select output for bank 0, or general-purpose i/o. memrd# output memory read signal for rom and system bus. memwr# output memory write signal for rom, dram and system bus. note the sysen# and sysdir signals control a buffer which is used to isolate sdram data bus from the bus of other low speed devices. by isolating the high-speed data bus of sdram, the load of the data bus between the v r 4181 and sdram is reduced. when the exbuffen bit of the xisactl register is cleared to 0, the sysen# and sysdir signals start their operation. these signals keep low level until exbuffen bit is cleared to 0 after a reset. when an isolation buffer is used, sysen# and sysdir signals function as follows; sysen# sysdir bus operation 0 0 external isa, compactflash, or rom read cycle 0 1 external isa, compactflash, or flash memory mode write cycle 1don ? t care external buffer disable dram read/write cycle or hibernate mode chapter 2 pin functions user ? s manual u14272ej3v0um 54 2.2.2 lcd interface signals signal name i/o description of function shclk/lcdcs# output lcd shift clock output or chip select for external lcd controller. loclk/memcs16# i/o lcd load clock output or bus sizing request input for system bus memory access. when using as memcs16#, the external agent must activate this signal at the system bus memory access in 16-bit width. flm/mips16en i/o the function of this pin differs depending on the operating status. chapter 2 pin functions user ? s manual u14272ej3v0um 55 2.2.3 initialization interface signals signal name i/o description of function power input v r 4181 activation signal. rstsw# input v r 4181 reset signal. rtcrst# input reset signal for internal real-time clock and internal logic. when power is first supplied to the system, the external agent must activate this signal. poweron output this signal indicates that the v r 4181 is ready to operate. it becomes active when a power-on factor is detected and becomes inactive when the battinh/battint# signal check has been completed. mpower output this signal indicates that the v r 4181 is operating. this signal is inactive during hibernate mode. during this signal being inactive, turn off the 2.5 v power supply. 2.2.4 battery monitor interface signals signal name i/o description of function battinh/battint# input the function of this pin differs depending on the state of the mpower pin. chapter 2 pin functions user ? s manual u14272ej3v0um 56 2.2.6 touch panel interface and audio interface signals signal name i/o description of function tpx(1:0) i/o touch panel x coordinate data. they use the voltage applied to the x coordinate and the voltage input to the y coordinate to detect which coordinates on the touch panel are being pressed. tpy(1:0) i/o touch panel y coordinate data. they use the voltage applied to the y coordinate and the voltage input to the x coordinate to detect which coordinates on the touch panel are being pressed. adin(2:0) input general-purpose a/d data inputs. audioin input audio input. audioout output audio output. 2.2.7 led interface signals signal name i/o description of function ledout output this is an output signal for lighting leds. 2.2.8 compactflash interface and keyboard interface signals signal name i/o description of function cf_we#/scanout7 output compactflash write enable output or keyboard scan data output. cf_oe#/scanout6 output compactflash output enable or keyboard scan data output. cf_iow#/scanout5 output compactflash i/o write strobe output or keyboard scan data output. cf_ior#/scanout4 output compactflash i/o read strobe output or keyboard scan data output. cf_stschg#/scanout3 i/o compactflash status changed input or keyboard scan data output. cf_ce(2:1)#/ scanout(2:1) output compactflash card enable outputs or keyboard scan data outputs. cf_busy#/scanout0 i/o compactflash ready/busy/interrupt request indication input or keyboard scan data output. cf_reg#/scanin7 i/o compactflash register select output or keyboard scan data input. cf_reset/scanin6 i/o compactflash reset output or keyboard scan data input. cf_wait#/scanin5 input compactflash wait input or keyboard scan data input. cf_iois16#/scanin4 input compactflash i/o 16-bit bus input or keyboard scan data input. cf_vccen#/scanin3 i/o compactflash v cc enable output or keyboard scan data input. cf_den#/scanin2 i/o compactflash data buffer enable output or keyboard scan data input. cf_dir/scanin1 i/o compactflash data direction control output or keyboard scan data input. cf_aen#/scanin0 i/o compactflash address buffer enable output or keyboard scan data input. chapter 2 pin functions user ? s manual u14272ej3v0um 57 2.2.9 serial interface channel 1 signals signal name i/o description of function rxd1/gpio25 i/o serial channel 1 receive data input or general-purpose i/o. txd1/gpio26/clksel0 i/o the function of this pin differs depending on the operating status. chapter 2 pin functions user ? s manual u14272ej3v0um 58 2.2.10 irda interface signals signal name i/o description of function irdin/rxd2 input irda receive data input or serial channel 2 receive data input. connect this pin to gnd (digital) via resistor when an irda receive component is connected. irdout/txd2 output irda transmit data output or serial channel 2 transmit data output. 2.2.11 general-purpose i/o signals signal name i/o description of function gpio(31:25) i/o see 2.2.9 serial interface channel 1 signals in this section gpio(24:16) i/o see 2.2.1 system bus interface signals in this section. gpio15/fpd7/cd2# i/o general-purpose i/o, lcd screen data output, or compactflash card detect 2 input. gpio14/fpd6/cd1# i/o general-purpose i/o, lcd screen data output, or compactflash card detect 1 input. gpio13/fpd5 i/o general-purpose i/o or lcd screen data output. gpio12/fpd4 i/o general-purpose i/o or lcd screen data output. gpio11/pcs1# i/o general-purpose i/o or programmable chip select 1. gpio10/frm/sysclk i/o general-purpose i/o, serial frame input for clocked serial interface, or external bus system clock output. gpio9/cts2# i/o general-purpose i/o or serial channel 2 clear to send output. gpio8/dsr2# i/o general-purpose i/o or serial channel 2 data set ready input. gpio7/dtr2# i/o general-purpose i/o or serial channel 2 data terminal ready input. gpio6/rts2# i/o general-purpose i/o or serial channel 2 request to send output. gpio5/dcd2# i/o general-purpose i/o or serial channel 2 data carrier detect input. gpio4 i/o general-purpose i/o. gpio3/pcs0# i/o general-purpose i/o or programmable chip select 0. gpio2/sck i/o general-purpose i/o or serial clock input for clocked serial interface. gpio1/so i/o general-purpose i/o or serial data output signal for clocked serial interface. gpio0/si i/o general-purpose i/o or serial data input signal for clocked serial interface. chapter 2 pin functions user ? s manual u14272ej3v0um 59 2.2.12 dedicated v dd /gnd signals signal name power supply description of function vdd_pll 2.5 v power supply dedicated for the pll analog block. gnd_pll 2.5 v ground dedicated for the pll analog block. vdd_tp 3.3 v power supply dedicated for the touch panel interface. gnd_tp 3.3 v ground dedicated for the touch panel interface. vdd_ad 3.3 v power supply dedicated for the a/d and d/a converters. the voltage applied to this pin becomes the maximum value for the a/d and d/a interface signals. gnd_ad 3.3 v ground dedicated for the a/d and d/a converters. the voltage applied to this pin becomes the minimum value for the a/d and d/a interface signals. vdd_osc 3.3 v power supply dedicated for the oscillator. gnd_osc 3.3 v ground dedicated for the oscillator. vdd_logic 2.5 v ordinary power supply of 2.5 v gnd_logic 2.5 v ordinary ground of 2.5 v vdd_io 3.3 v ordinary power supply of 3.3 v gnd_io 3.3 v ordinary ground of 3.3 v caution the v r 4181 has two types of power supplies. the 3.3 v power supply should be turned on at first. turn on/off the 2.5 v power supply depending on the status of the mpower pin. chapter 2 pin functions user ? s manual u14272ej3v0um 60 2.3 pin status in specific status (1/3) signal name during rtc reset after rtc reset after reset by deadman ? s switch or rstsw during suspend mode during hibernate mode or shutdown by haltimer add(21:0) hi-z 0 0 note 1 0 data(15:0) hi-z hi-z hi-z hi-z hi-z memrd# hi-z 1 1 1 hi-z memwr# hi-z 1 1 1 1 sdcs(1:0)#/ras(1:0)# hi-z 1 1 1/0 note2 1/0 note2 udqm/ucas# hi-z 1 1 1/0 note2 1/0 note2 ldqm/lcas# hi-z 1 1 1/0 note2 1/0 note2 cas# hi-z 1 1 0 0 sdras# hi-z 1 1 0 0 sdclk hi-z run 0 0 0 clken hi-z 1 1 1 0 sysdir hi-z 0 0 0 0 sysen# hi-z 0 0 0 0 iord#/gpio16 ? hi-z hi-z 1/ note 1 hi-z/ note 3 iowr#/gpio17 ? hi-z hi-z 1/ note 1 hi-z/ note 3 iordy/gpio18 ? hi-z hi-z note 1 note 3 iocs16#/gpio19 ? hi-z hi-z note 1 note 3 ube#/gpio20/m ? hi-z hi-z 1/ note 1 /0 hi-z/ note 3 /0 reset#/gpio21 ? hi-z hi-z note 1 0/ note 3 romcs(2:0)#/gpio(24:22) ? hi-z hi-z 1/ note 1 hi-z/ note 3 romcs3# hi-z hi-z 1 1 hi-z shclk/lcdcs# hi-z 0 0/1 0/1 0/hi-z loclk/memcs16# hi-z 0 0/ ? 0/ ? 0/ ? flm/mips16en note 4 0000 fpd(3:0) hi-z 0 0 0 0 vplcd/vpgpio1 hi-z hi-z hi-z hi-z hi-z vpbias/vpgpio0 hi-z hi-z hi-z hi-z hi-z power ????? rtcrst# ????? rstsw# ????? notes1. maintains the state of the previous fullspeed mode. 2. the state depends on the memcfg_reg register setting. 3. the state depends on the gphibsth/gphibstl register setting. 4. the input level is sampled to determine the mips16 instruction mode. remark 0: low level, 1: high level, hi-z: high impedance chapter 2 pin functions user ? s manual u14272ej3v0um 61 (2/3) signal name during rtc reset after rtc reset after reset by deadman ? s switch or rstsw during suspend mode during hibernate mode or shutdown by haltimer poweron ?? 000 mpower 00110 battinh/battint# ????? rtcx2, rtcx1 ????? clkx2, clkx1 ????? tpx(1:0) ? 11 note 1 1 tpy(1:0) ? hi-z hi-z note 1 hi-z adin(2:0) ????? audioin ????? audioout ? 00 note 1 0 cf_we#/scanout7 hi-z hi-z hi-z note 1 note 2 /hi-z cf_oe#/scanout6 hi-z hi-z hi-z note 1 note 2 /hi-z cf_iow#/scanout5 hi-z hi-z hi-z note 1 note 2 /hi-z cf_ior#/scanout4 hi-z hi-z hi-z note 1 note 2 /hi-z cf_stschg#/scanout3 hi-z hi-z hi-z note 1 note 1 /hi-z cf_ce(2:1)#/ scanout(2:1) hi-z hi-z hi-z note 1 note 2 /hi-z cf_busy#/scanout0 hi-z hi-z hi-z note 1 note 1 /hi-z cf_reg#/scanin7 hi-z ? note 1 note 1 note 2 / note 1 cf_reset/scanin6 hi-z ? note 1 note 1 note 3 / note 1 cf_wait#/scanin5 ?? note 1 note 1 ? cf_iois16#/scanin4 ?? note 1 note 1 ? cf_vccen#/scanin3 hi-z ? note 1 note 1 note 4 / note 1 cf_den#/scanin2 hi-z ? note 1 note 1 1/ note 1 cf_dir/scanin1 hi-z ? note 1 note 1 1/ note 1 cf_aen#/scanin0 hi-z ? note 1 note 1 1/ note 1 notes1. maintains the state of the previous fullspeed mode. 2. when cf wake-up is enabled: outputs high level. when cf wake-up is disabled: becomes high impedance. 3. when cf wake-up is enabled: outputs low level. when cf wake-up is disabled: becomes high impedance. 4. when cf wake-up is enabled: outputs low level. when cf wake-up is disabled: outputs high level. remark 0: low level, 1: high level, hi-z: high impedance chapter 2 pin functions user ? s manual u14272ej3v0um 62 (3/3) signal name during rtc reset after rtc reset after reset by deadman ? s switch or rstsw during suspend mode during hibernate mode or shutdown by haltimer rxd1/gpio25 ? hi-z hi-z note 1 note 1 / note 2 txd1/gpio26/clksel0 note 3 hi-z hi-z note 1 note 1 / note 2 rts1#/gpio27/clksel1 note 3 hi-z hi-z note 1 note 1 / note 2 cts1#/gpio28 ? hi-z hi-z note 1 note 1 / note 2 dcd1#/gpio29 ? hi-z hi-z note 1 note 1 / note 2 dtr1#/gpio30/clksel2 note 3 hi-z hi-z note 1 note 1 / note 2 dsr1#/gpio31 ? hi-z hi-z note 1 note 1 / note 2 irdin/rxd2 ????? irdout/txd2 hi-z hi-z 1 note 1 hi-z gpio(15:14)/fpd(7:6)/ cd(2:1)# ? hi-z hi-z note 1 /0/ note 1 note 2 / note 1 gpio(13:12)/fpd(5:4) ? hi-z hi-z note 1 /0 note 2 / note 1 gpio11/pcs1# ? /hi-z hi-z hi-z/1 note 1 /1 note 2 /hi-z gpio10/frm/sysclk ? /hi-z hi-z hi-z note 1 /0 note 2 / note 1 / hi-z gpio9/cts2# ? hi-z hi-z note 1 note 2 / note 1 gpio8/dsr2# ? hi-z hi-z note 1 note 2 / note 1 gpio7/dtr2# ? hi-z hi-z note 1 note 2 / note 1 gpio6/rts2# ? hi-z hi-z note 1 note 2 / note 1 gpio5/dcd2# ? hi-z hi-z note 1 note 2 / note 1 gpio4 ? hi-z hi-z note 1 note 2 gpio3/pcs0# ? /hi-z hi-z hi-z/1 note 1 /1 note 2 /hi-z gpio2/sck ? hi-z hi-z note 1 note 2 / note 1 gpio1/so ? hi-z hi-z note 1 note 2 / note 1 gpio0/si ? hi-z hi-z note 1 note 2 / note 1 ledout hi-z 1 note 1 note 1 note 1 notes1. maintains the state of previous fullspeed mode. 2. the state depends on the gphibsth/gphibstl register setting. 3. the input level is sampled to determine the cpu core operation frequency. remark 0: low level, 1: high level, hi-z: high impedance chapter 2 pin functions user ? s manual u14272ej3v0um 63 2.4 recommended connection of unused pins and i/o circuit types (1/3) pin name recommended connection when not used i/o circuit type add(21:0) ? a data(15:0) ? a memrd# ? a memwr# ? a sdcs(1:0)#/ras(1:0)# ? a udqm/ucas# ? a ldqm/lcas# ? a cas# leave open a sdras# leave open a sdclk leave open a clken leave open a sysdir leave open a sysen# leave open a iord#/gpio16 connect to vdd_io or gnd_io via resistor a iowr#/gpio17 connect to vdd_io or gnd_io via resistor a iordy/gpio18 connect to vdd_io or gnd_io via resistor a iocs16#/gpio19 connect to vdd_io or gnd_io via resistor a ube#/gpio20/m connect to vdd_io or gnd_io via resistor a reset#/gpio21 connect to vdd_io or gnd_io via resistor a romcs(2:0)#/gpio(24:22) connect to vdd_io or gnd_io via resistor a romcs3# ? a shclk/lcdcs# leave open a loclk/memcs16# leave open a flm/mips16en connect to vdd_io or gnd_io via resistor a fpd(3:0) leave open a vplcd/vpgpio1 leave open a vpbias/vpgpio0 leave open a power connect to gnd_io via resistor a rtcrst# ? a rstsw# ? a poweron leave open a mpower ? a battinh/battint# ? a tpx(1:0) ? b tpy(1:0) ? c remark no specification ( ? ) in the recommended connection when not used column indicates that the pin is always connected. chapter 2 pin functions user ? s manual u14272ej3v0um 64 (2/3) pin name recommended connection when not used i/o circuit type adin(2:0) connect to gnd_ad d audioin connect to gnd_ad d audioout leave open e cf_we#/scanout7 leave open a cf_oe#/scanout6 leave open a cf_iow#/scanout5 leave open a cf_ior#/scanout4 leave open a cf_stschg#/scanout3 connect to vdd_io via resistor a cf_ce(2:1)#/scanout(2:1) leave open a cf_busy#/scanout0 connect to vdd_io via resistor a cf_reg#/scanin7 leave open a cf_reset/scanin6 leave open a cf_wait#/scanin5 connect to vdd_io via resistor a cf_iois16#/scanin4 connect to vdd_io via resistor a cf_vccen#/scanin3 leave open a cf_den#/scanin2 leave open a cf_dir/scanin1 leave open a cf_aen#/scanin0 leave open a rxd1/gpio25 connect to vdd_io or gnd_io via resistor a txd1/gpio26/clksel0 connect to vdd_io or gnd_io via resistor a rts1#/gpio27/clksel1 connect to vdd_io or gnd_io via resistor a cts1#/gpio28 connect to vdd_io or gnd_io via resistor a dcd1#/gpio29 connect to vdd_io or gnd_io via resistor a dtr1#/gpio30/clksel2 connect to vdd_io or gnd_io via resistor a dsr1#/gpio31 connect to vdd_io or gnd_io via resistor a irdin/rxd2 connect to vdd_io or gnd_io via resistor a irdout/txd2 leave open a gpio(15:14)/fpd(7:6)/cd(2:1)# connect to vdd_io or gnd_io via resistor a gpio(13:12)/fpd(5:4) connect to vdd_io or gnd_io via resistor a gpio11/pcs1# connect to vdd_io or gnd_io via resistor a gpio10/frm/sysclk connect to vdd_io or gnd_io via resistor a gpio9/cts2# connect to vdd_io or gnd_io via resistor a gpio8/dsr2# connect to vdd_io or gnd_io via resistor a gpio7/dtr2# connect to vdd_io or gnd_io via resistor a gpio6/rts2# connect to vdd_io or gnd_io via resistor a gpio5/dcd2# connect to vdd_io or gnd_io via resistor a gpio4 connect to vdd_io or gnd_io via resistor a chapter 2 pin functions user ? s manual u14272ej3v0um 65 (3/3) pin name recommended connection when not used i/o circuit type gpio3/pcs0# connect to vdd_io or gnd_io via resistor a gpio2/sck connect to vdd_io or gnd_io via resistor a gpio1/so connect to vdd_io or gnd_io via resistor a gpio0/si connect to vdd_io or gnd_io via resistor a ledout leave open a chapter 2 pin functions user ? s manual u14272ej3v0um 66 2.5 pin i/o circuits + ? + ? + ? output disable input enable data output disable data input enable analog output voltage out output disable data v ref v ref v ref v dd p-ch n-ch in/out v dd p-ch n-ch p-ch n-ch in/out v dd p-ch n-ch n-ch p-ch in n-ch p-ch n-ch in/out type a type c type d type e type b user?s manual u14272ej3v0um 67 chapter 3 cp0 registers 3.1 coprocessor 0 (cp0) the coprocessor 0 (cp0), which is also called as system control coprocessor, is implemented as an integral part of the cpu, and supports memory management, address translation, exception handling, and operation mode control. memory management, address translation, and operation mode control are provided by a block called memory management unit (mmu). the mmu contains a 32-entry tlb (translation lookaside buffer) that is used when translating virtual addresses to physical addresses. the cp0 has registers shown in table 3-1 that are used to set various modes for memory management and exception handling and to indicate statuses of the processor. each cp0 register has a unique number that is used as an operand to specify a cp0 register to be accessed. caution when accessing the cp0 registers, some instructions require consideration of the interval time until the next instruction is executed, because there is a delay from when the contents of the cp0 register change to when this change is reflected in the cpu operation. this time lag is called a cp0 hazard. for details, refer to chapter 23 coprocessor 0 hazards. for details about functions of the cp0, refer to v r 4100 series architecture user?s manual . chapter 3 cp0 registers user?s manual u14272ej3v0um 68 table 3-1. cp0 registers number register usage description 0 index memory management programmable pointer to tlb array 1 random memory management pseudo-random pointer to tlb array (read only) 2 entrylo0 memory management lower half of tlb entry for even vpn 3 entrylo1 memory management lower half of tlb entry for odd vpn 4 context exception processing pointer to kernel virtual pte in 32-bit mode 5 pagemask memory management page size specification 6 wired memory management number of wired tlb entries 7 ?? reserved for future use 8 badvaddr exception processing virtual address where the most recent error occurred 9 count exception processing timer count 10 entryhi memory management higher half of tlb entry (including asid) 11 compare exception processing timer compare value 12 status exception processing status indication 13 cause exception processing cause of last exception 14 epc exception processing exception program counter 15 prid memory management processor revision identifier 16 config memory management configuration (memory system m odes) specification 17 lladdr note1 memory management physical address for self diagnostics 18 watchlo exception processing memory reference trap address low bits 19 watchhi exception processing memory reference trap address high bits 20 xcontext exception processing pointer to kernel virtual pte in 64-bit mode 21 to 25 ?? reserved for future use 26 parity error note2 exception processing cache parity bits 27 cache error note2 exception processing index and status of cache error 28 taglo memory management lower half of cache tag 29 taghi memory management higher half of cache tag 30 errorepc exception processing error exception program counter 31 ?? reserved for future use notes1. this register is defined to maintain compatibility with the v r 4000 and v r 4400. this register is meaningless during normal operations. 2. this register is defined to maintain compatibility with the v r 4100. this register is not used in the v r 4181 hardware. chapter 3 cp0 registers user?s manual u14272ej3v0um 69 3.2 details of cp0 registers 3.2.1 index register (0) the index register is a 32-bit, read/write register containing five low-order bits to index an entry in the tlb. the most-significant bit of the register shows the success or failure of a tlb probe (tlbp) instruction. the index register also specifies the tlb entry affected by tlb read (tlbr) or tlb write index (tlbwi) instructions. the contents of the index register are undefined after a reset so that it must be initialized by software. figure 3-1. index register 31 p 0 index 30 5 4 0 p: indicates whether probing is successful or not. it is set to 1 if the latest tlbp instruction fails. it is cleared to 0 when the tlbp instruction is successful. index: specifies an index to a tlb entry that is a target of the tlbr or tlbwi instruction. 0: reserved for future use. write 0 in a write operation. when this field is read, 0 is read. 3.2.2 random register (1) the random register is a read-only register. the low-order 5 bits are used in referencing a tlb entry. this register is decremented each time an instruction is executed. the values that can be set in the register are as follows: ? the lower bound is the content of the wired register. ? the upper bound is 31. the random register specifies the entry in the tlb that is affected by the tlbwr instruction. the register is readable to verify proper operation of the processor. the random register is set to the value of the upper bound upon cold reset. this register is also set to the upper bound when the wired register is written. figure 3-2 shows the format of the random register. figure 3-2. random register 31 0 random 54 0 random: tlb random index 0: reserved for future use. write 0 in a write operation. when this field is read, 0 is read. chapter 3 cp0 registers user ? s manual u14272ej3v0um 70 3.2.3 entrylo0 (2) and entrylo1 (3) registers the entrylo register consists of two registers that have identical formats: entrylo0, used for even virtual pages and entrylo1, used for odd virtual pages. the entrylo0 and entrylo1 registers are both read-/write-accessible. they are used to access the built-in tlb. when a tlb read/write operation is carried out, the entrylo0 and entrylo1 registers hold the contents of the low-order 32 bits of tlb entries at even and odd addresses, respectively. the contents of these registers are undefined after a reset so that they must be initialized by software. figure 3-3. entrylo0 and entrylo1 registers (a) 32-bit mode (b) 64-bit mode 31 28 27 6 5 3 2 1 0 pfn c d v g 0 entrylo0 31 28 27 6 5 3 2 1 0 pfn c d v g 0 entrylo1 63 28 27 6 5 3 2 1 0 pfn c d v g 0 entrylo0 63 28 27 6 5 3 2 1 0 pfn c d v g 0 entrylo1 pfn: page frame number; high-order bits of the physical address. c: specifies the tlb page attribute (see table 3-2 ). d: dirty. if this bit is set to 1, the page is marked as dirty and, therefore, writable. this bit is actually a write-protect bit that software can use to prevent alteration of data. v: valid. if this bit is set to 1, it indicates that the tlb entry is valid; otherwise, a tlb invalid exception (tlbl or tlbs) occurs. g: global. if this bit is set in both entrylo0 and entrylo1, then the processor ignores the asid during tlb lookup. 0: reserved for future use. write 0 in a write operation. when this field is read, 0 is read. the coherency attribute (c) bits are used to specify whether to use the cache in referencing a page. when the cache is used, whether the page attribute is ? cached ? or ? uncached ? is selected by algorithm. table 3-2 lists the page attributes selected according to the value in the c bits. chapter 3 cp0 registers user ? s manual u14272ej3v0um 71 table 3-2. cache algorithm c bit value cache algorithm 0 cached 1 cached 2 uncached 3 cached 4 cached 5 cached 6 cached 7 cached 3.2.4 context register (4) the context register is a read/write register containing the pointer to an entry in the page table entry (pte) array on the memory; this array is a table that stores virtual-to-physical address translations. when there is a tlb miss, the operating system loads the unsuccessfully translated entry from the pte array to the tlb. the context register is used by the tlb refill exception handler for loading tlb entries. the context register duplicates some of the information provided in the badvaddr register, but the information is arranged in a form that is more useful for a software tlb exception handler. figure 3-4. context register (a) 32-bit mode (b) 64-bit mode 0 24 24 25 31 4 3 ptebase badvpn2 0 0 25 63 4 3 ptebase badvpn2 0 ptebase: the ptebase field is a base address of the pte entry table. badvpn2: this field holds the value (vpn2) obtained by halving the virtual page number of the most recent virtual address for which translation failed. 0: reserved for future use. write 0 in a write operation. when this field is read, 0 is read. the ptebase field is used by software as the pointer to the base address of the pte table in the current user address space. the 21-bit badvpn2 field contains bits 31 to 11 of the virtual address that caused the tlb miss; bit 10 is excluded because a single tlb entry maps to an even-odd page pair. for a 1 kb page size, this format can directly address the pair-table of 8-byte ptes. when the page size is 4 kb or more, shifting or masking this value produces the correct pte reference address. chapter 3 cp0 registers user ? s manual u14272ej3v0um 72 3.2.5 pagemask register (5) the pagemask register is a read/write register used for reading from or writing to the tlb; it holds a comparison mask that sets the page size for each tlb entry, as shown in table 3-3. five page sizes can be selected between 1 kb and 256 kb. tlb read and write instructions use this register as either a source or a destination; bits 18 to 11 that are targets of comparison are masked during address translation. the contents of the pagemask register are undefined after a reset so that it must be initialized by software. figure 3-5. pagemask register 31 19 18 11 10 0 mask 0 0 mask: page comparison mask, which determines the virtual page size for the corresponding entry. 0: reserved for future use. write 0 in a write operation. when this field is read, 0 is read. table 3-3 lists the mask pattern for each page size. if the mask pattern is one not listed below, the tlb behaves unexpectedly. table 3-3. mask values and page sizes page size bit 18 17 16 15 14 13 12 11 1 kb 00000000 4 kb 00000011 16 kb 00001111 64 kb 00111111 256 kb 1 1111111 chapter 3 cp0 registers user ? s manual u14272ej3v0um 73 3.2.6 wired register (6) the wired register is a read/write register that specifies the lower boundary of the random entry of the tlb as shown in figure 3-6. wired entries cannot be overwritten by a tlbwr instruction, but by a tlbwi instruction. random entries can be overwritten by both instructions. figure 3-6. positions indicated by the wired register 31 value in the wired register 0 range specified by the random register range of wired entries tlb the wired register is set to 0 upon cold reset. writing this register also sets the random register to the value of its upper bound (see 3.2.2 random register (1) ). figure 3-7. wired register 31 5 4 0 0 wired wired: tlb wired boundary 0: reserved for future use. write 0 in a write operation. when this field is read, 0 is read. chapter 3 cp0 registers user ? s manual u14272ej3v0um 74 3.2.7 badvaddr register (8) the bad virtual address (badvaddr) register is a read-only register that saves the most recent virtual address that failed to have a valid translation, or that had an addressing error. caution this register saves no information after a bus error exception, because it is not an address error exception. figure 3-8. badvaddr register (a) 32-bit mode 0 31 badvaddr (b) 64-bit mode 0 63 badvaddr badvaddr: most recent virtual address for which an addressing error occurred, or for which address translation failed. 3.2.8 count register (9) the read/write count register acts as a timer. it is incremented in synchronization with the masterout clock (1/8, 1/12, or 1/16 frequencies of the pclock), regardless of whether instructions are being executed, retired, or any forward progress is actually made through the pipeline. this register is a free-running type. when the register reaches all ones, it rolls over to zero and continues counting. this register is used for self-diagnostic test, system initialization, or the establishment of inter-process synchronization. figure 3-9. count register 0 31 count count: up-to-date count value that is compared with the value of the compare register. chapter 3 cp0 registers user ? s manual u14272ej3v0um 75 3.2.9 entryhi register (10) the entryhi register is write-accessible. it is used to access the built-in tlb. the entryhi register holds the high- order bits of a tlb entry for tlb read and write operations. if a tlb refill, tlb invalid, or tlb modified exception occurs, the entryhi register holds the high-order bit of the tlb entry. the entryhi register is also set with the virtual page number (vpn2) for a virtual address where an exception occurred and the asid. see v r 4100 series architecture user ? s manual for details of the tlb exception. the asid is used to read from or write to the asid field of the tlb entry. it is also checked with the asid of the tlb entry as the asid of the virtual address during address translation. the entryhi register is accessed by the tlbp, tlbwr, tlbwi, and tlbr instructions. the contents of the entryhi register are undefined after a reset so that it must be initialized by software. figure 3-10. entryhi register 31 11 10 8 7 0 (a) 32-bit mode (b) 64-bit mode vpn2 0 asid 63 62 61 11 10 40 39 8 7 0 fill vpn2 r 0 asid vpn2: virtual page number divided by two (mapping to two pages) asid: address space id. an 8-bit asid field that allows multiple processes to share the tlb; each process has a distinct mapping of otherwise identical virtual page numbers. r: space type (00 user, 01 supervisor, 11 kernel). matches bits 63 and 62 of the virtual address. fill: reserved. ignored on write. when read, returns zero. 0: reserved for future use. write 0 in a write operation. when this field is read, 0 is read. chapter 3 cp0 registers user ? s manual u14272ej3v0um 76 3.2.10 compare register (11) the compare register causes a timer interrupt; it maintains a stable value that does not change on its own. when the value of the count register (see 3.2.8 count register (9) ) equals the value of the compare register, the ip7 bit in the cause register is set. this causes an interrupt as soon as the interrupt is enabled. writing a value to the compare register, as a side effect, clears the timer interrupt request. for diagnostic purposes, the compare register is a read/write register. normally, this register should be only used for a write. the contents of the compare register are undefined after a reset. figure 3-11. compare register 0 31 compare compare: value that is compared with the count value of the count register. 3.2.11 status register (12) the status register is a read/write register that contains the operating mode, interrupt enabling, and the diagnostic states of the processor. figure 3-12. status register (1/2) 292827262524 1615 8765 3210 31 0 cu0 0 re ds im ux ksu erl ie kx sx exl 4 cu0: enables/disables the use of the coprocessor (1 enabled, 0 disabled). cp0 can be used in kernel mode at all times. re: enables/disables reversing of the endian setting in user mode (0 disabled, 1 enabled). this bit must be set to 0 since the v r 4181 supports the little-endian order only. ds: diagnostic status field (see figure 3-13 ). im: interrupt mask field used to enable/disable interrupts (0 disabled, 1 enabled). this field consists of 8 bits that are used to control eight interrupts. the bits are assigned to interrupts as follows: im7: masks a timer interrupt. im(6:2): mask ordinary interrupts (int(4:0) note ). however, int(4:3) note never occur in the v r 4181. im(1:0): mask software interrupts. note int(4:0) are internal signals of the v r 4110 cpu core. for details about connection to the on-chip peripheral units, refer to chapter 9 interrupt control unit (icu) . chapter 3 cp0 registers user ? s manual u14272ej3v0um 77 figure 3-12. status register (2/2) kx: enables 64-bit addressing in kernel mode (0 32-bit, 1 64-bit). 64-bit operations are always valid in kernel mode. sx: enables 64-bit addressing and operation in supervisor mode (0 32-bit, 1 64-bit). ux: enables 64-bit addressing and operation in user mode (0 32-bit, 1 64-bit). ksu: sets and indicates the operating mode (10 user, 01 supervisor, 00 kernel). erl: sets and indicates the error level (0 normal, 1 error). exl: sets and indicates the exception level (0 normal, 1 exception). ie: sets and indicates interrupt enabling/disabling (0 disabled, 1 enabled). 0: reserved for future use. write 0 in a write operation. when this bit is read, 0 is read. figure 3-13 shows the details of the diagnostic status (ds) field. all ds field bits other than the ts bit are writable. figure 3-13. status register diagnostic status field 16 17 18 19 20 21 22 23 24 0 bev ts sr 0 ch ce de bev: specifies the base address of a tlb refill exception vector and common exception vector (0 normal, 1 bootstrap). ts: occurs the tlb to be shut down (read-only) (0 not shut down, 1 shut down). this bit is used to avoid any problems that may occur when multiple tlb entries match the same virtual address. after the tlb has been shut down, reset the processor to enable restart. note that the tlb is shut down even if a tlb entry matching a virtual address is marked as being invalid (with the v bit cleared). sr: occurs a soft reset or nmi exception (0 not occurred, 1 occurred). ch: cp0 condition bit (0 false, 1 true). this bit can be read and written by software only; it cannot be accessed by hardware. ce, de: these are prepared to maintain compatibility with the v r 4100, and are not used in the v r 4181 hardware. 0: reserved for future use. write 0 in a write operation. when this field is read, 0 is read. the status register has the following fields where the modes and access statuses are set. chapter 3 cp0 registers user ? s manual u14272ej3v0um 78 (1) interrupt enable interrupts are enabled when all of the following conditions are true: ? ie bit is set to 1. ? exl bit is cleared to 0. ? erl bit is cleared to 0. ? the appropriate bit of the im field is set to 1. (2) operating modes the following status register bit settings are required for user, kernel, and supervisor modes. ? the processor is in user mode when ksu = 10, exl = 0, and erl = 0. ? the processor is in supervisor mode when ksu = 01, exl = 0, and erl = 0. ? the processor is in kernel mode when ksu = 00, exl = 1, or erl = 1. access to the kernel address space is allowed when the processor is in kernel mode. access to the supervisor address space is allowed when the processor is in supervisor or kernel mode. access to the user address space is allowed in any of the three operating modes. (3) addressing modes the following status register bit settings select 32- or 64-bit operation for each of user, kernel, and supervisor operating modes. enabling 64-bit operation permits the execution of 64-bit opcodes and translation of 64-bit addresses. 64-bit operation for user, kernel and supervisor modes can be set independently. ? 64-bit addressing for kernel mode is enabled when kx bit = 1. 64-bit operations are always valid in kernel mode. if this bit is set, an xtlb refill exception occurs if a tlb miss occurs in the kernel mode address space. ? 64-bit addressing and operations are enabled for supervisor mode when sx bit = 1. if this bit is set, an xtlb refill exception occurs if a tlb miss occurs in the supervisor mode address space. ? 64-bit addressing and operations are enabled for user mode when ux bit = 1. if this bit is set, an xtlb refill exception occurs if a tlb miss occurs in the user mode address space. (4) status after reset the contents of the status register are undefined after cold resets, except for the following bits in the diagnostic status field. ? ts and sr bits are cleared to 0. sr bit is 0 after cold reset, and is 1 after soft reset or nmi. ? erl and bev bits are set to 1. remark cold reset and soft reset are resets for the cpu core (see 5.3 reset of cpu core ). for the reset of all the v r 4181 including peripheral units, refer to chapter 5 initialization interface and chapter 10 power management unit (pmu) . chapter 3 cp0 registers user ? s manual u14272ej3v0um 79 3.2.12 cause register (13) the 32-bit read/write cause register holds the cause of the most recent exception. a 5-bit exception code indicates one of the causes (see table 3-4 ). other bits hold the detailed information of the specific exception. all bits in the cause register, with the exception of the ip1 and ip0 bits, are read-only; ip1 and ip0 bits are used for software interrupts. figure 3-14. cause register 8 27 16 15 6 7210 31 30 29 28 bd 0 ce 0 ip(7:0) 0 exccode 0 bd: indicates whether the most recent exception occurred in the branch delay slot (1 in delay slot, 0 normal). ce: indicates the coprocessor number in which a coprocessor unusable exception occurred. this field will remain undefined for as long as no exception occurs. ip: indicates whether an interrupt is pending (1 interrupt pending, 0 no interrupt pending). ip7: a timer interrupt. ip(6:2): ordinary interrupts (int(4:0) note ). however, int(4:3) note never occurs in the v r 4181. ip(1:0): software interrupts. only these bits cause an interrupt exception, when they are set to 1 by means of software. note int(4:0) are internal signals of the v r 4110 cpu core. for details about connection to the on-chip peripheral units, refer to chapter 9 interrupt control unit (icu) . exccode: exception code field (refer to table 3-4 for details). 0: reserved for future use. write 0 in a write operation. when this field is read, 0 is read. chapter 3 cp0 registers user ? s manual u14272ej3v0um 80 table 3-4. cause register exception code field exception code mnemonic description 0 int interrupt exception 1 mod tlb modified exception 2 tlbl tlb refill exception (load or fetch) 3 tlbs tlb refill exception (store) 4 adel address error exception (load or fetch) 5 ades address error exception (store) 6 ibe bus error exception (instruction fetch) 7 dbe bus error exception (data load or store) 8 sys system call exception 9 bp breakpoint exception 10 ri reserved instruction exception 11 cpu coprocessor unusable exception 12 ov integer overflow exception 13 tr trap exception 14 to 22 ? reserved for future use 23 watch watch exception 24 to 31 ? reserved for future use the v r 4181 has eight interrupt request sources, ip7 to ip0. they are used for the purpose as follows. for the detailed description of interrupts of the cpu core, refer to v r 4100 series architecture user ? s manual . (1) ip7 this bit indicates whether there is a timer interrupt request. it is set when the values of the count register and compare register match. (2) ip6 to ip2 ip6 to ip2 reflect the state of the interrupt request signals of the cpu core. (3) ip1 and ip0 these bits are used to set/clear a software interrupt request. chapter 3 cp0 registers user ? s manual u14272ej3v0um 81 3.2.13 exception program counter (epc) register (14) the exception program counter (epc) is a read/write register that contains the address at which processing resumes after an exception has been serviced. the contents of this register change depending on whether execution of mips16 instructions is enabled or disabled. setting the mips16en pin after rtc reset specifies whether execution of the mips16 instructions is enabled or disabled. when the mips16 instruction execution is disabled, either of the following addresses is contained in the epc register: ? virtual address of the instruction that caused the exception ? virtual address of the immediately preceding branch or jump instruction (when the instruction associated with the exception is in a branch delay slot, and the bd bit in the cause register is set to 1) when the mips16 instruction execution is enabled, either of the following addresses is contained in the epc register during a 32-bit instruction execution: ? virtual address of the instruction that caused the exception and isa mode at which an exception occurs ? virtual address of the immediately preceding branch or jump instruction and isa mode at which an exception occurs (when the instruction associated with the exception is in a branch delay slot of the jump instruction, and the bd bit in the cause register is set to 1) when the 16-bit instruction is executed, either of the following addresses is contained in the epc register: ? virtual address of the instruction that caused the exception and isa mode at which an exception occurs ? virtual address of the immediately preceding extend or jump instruction and isa mode at which an exception occurs (when the instruction associated with the exception is in a branch delay slot of the jump instruction or in the instruction following the extend instruction, and the bd bit in the cause register is set to 1) the exl bit in the status register is set to 1 to keep the processor from overwriting the address of the exception- causing instruction contained in the epc register in the event of another exception. the epc register never indicates the address of the instruction in a branch delay slot. figure 3-15. epc register (when mips16 isa is disabled) 0 31 epc (a) 32-bit mode (b) 64-bit mode 0 63 epc epc: restart address (virtual) after exception processing. chapter 3 cp0 registers user ? s manual u14272ej3v0um 82 figure 3-16. epc register (when mips16 isa is enabled) 1 (a) 32-bit mode 0 31 epc eim epc: bits 31 to 1 of restart address (virtual) after exception processing. eim: isa mode at which an exception occurs (1 when mips16 sia instruction is executed, 0 when mips iii isa instruction is executed). 1 (b) 64-bit mode 0 63 epc eim epc: bits 63 to 1 of restart address (virtual) after exception processing. eim: isa mode at which an exception occurs (1 when mips16 sia instruction is executed, 0 when mips iii isa instruction is executed). 3.2.14 processor revision identifier (prid) register (15) the 32-bit, read-only processor revision identifier (prid) register contains information identifying the implementation and revision level of the cpu and cp0. figure 3-17. prid register 31 16 15 8 7 0 0 imp rev imp: cpu core processor id number (0x0c for the v r 4181) rev: cpu core processor revision number 0: reserved for future use. write 0 in a write operation. when this field is read, 0 is read. the processor revision number is stored as a value in the form y.x, where y is a major revision number in bits 7 to 4 and x is a minor revision number in bits 3 to 0. the processor revision number can distinguish cpu core revisions of the v r 4181, however there is no guarantee that changes to the cpu core will necessarily be reflected in the prid register, or that changes to the revision number necessarily reflect real cpu core changes. therefore, create a program that does not depend on the processor revision number field. chapter 3 cp0 registers user ? s manual u14272ej3v0um 83 3.2.15 config register (16) the config register specifies various configuration options selected on the v r 4181. some configuration options, as defined by the ec and be fields, are set by the hardware during cold reset and are included in the config register as read-only status bits for the software to access. other configuration options (ad, ep, and k0 fields) can be read/written and controlled by software; on cold reset these fields are undefined. since only a subset of the v r 4000 series tm options are available in the v r 4181, some bits are set to constants (e.g., bits 14 and 13) that were variable in the v r 4000 series. the config register should be initialized by software before caches are used. the contents of the config register are undefined after a reset so that it must be initialized by software. caution be sure to set the ep field and the ad bit to 0. if they are set with any other values, the processor may behave unexpectedly. figure 3-18. config register (1/2) 31 30 28 27 24 23 22 21 20 19 18 17 16 15 14 13 12 11 9 8 6 5 3 2 0 0ec epad0 m16 010be10cs ic dc 0 k0 ec: system clock ratio (read only) 0 processor clock frequency divided by 2 1 processor clock frequency divided by 3 2 processor clock frequency divided by 4 3 to 7 reserved ep: transfer data pattern (cache write-back pattern) setting 0 dd: 1 word per 1 cycle others reserved ad: accelerate data mode 0 v r 4000 series compatible mode 1 reserved m16: mips16 isa mode enable/disable indication (read only) 0 mips16 instruction cannot be executed 1 mips16 instruction can be executed. be: bigendianmem (endian mode indication) 0 little endian 1 reserved cs: cache size mode indication (n = ic, dc) 0 reserved 1 2 (n+10) bytes ic: instruction cache size indication. 2 (ic+10) bytes in the v r 4181. 2 4 kb others reserved dc: data cache size indication. 2 (dc+10) bytes in the v r 4181. 2 4 kb others reserved chapter 3 cp0 registers user ? s manual u14272ej3v0um 84 figure 3-18. config register (2/2) k0: kseg0 cache coherency algorithm 2 uncached others cached 1: 1 is returned when read. 0: 0 is returned when read. 3.2.16 load linked address (lladdr) register (17) the read/write load linked address (lladdr) register is not used with the v r 4181 processor except for diagnostic purpose, and serves no function during normal operation. the lladdr register is implemented just for compatibility between the v r 4181 and v r 4000 or v r 4400. the contents of the lladdr register are undefined after a reset. figure 3-19. lladdr register 31 0 paddr paddr: 32-bit physical address chapter 3 cp0 registers user ? s manual u14272ej3v0um 85 3.2.17 watchlo (18) and watchhi (19) registers the v r 4181 processor provides a debugging feature to detect references to a selected physical address; load and store instructions to the location specified by the watchlo and watchhi registers cause a watch exception. the contents of these registers are undefined after a reset so that they must be initialized by software. figure 3-20. watchlo register 3210 31 paddr0 0 r w paddr0: specifies physical address bits 31 to 3. r: specifies detection of watch address references when load instructions are executed (1 detect, 0 not detect). w: specifies detection of watch address references when store instructions are executed (1 detect, 0 not detect). 0: reserved for future use. write 0 in a write operation. when this field is read, 0 is read. figure 3-21. watchhi register 0 31 0 0: reserved for future use. write 0 in a write operation. when this field is read, 0 is read. chapter 3 cp0 registers user ? s manual u14272ej3v0um 86 3.2.18 xcontext register (20) the read/write xcontext register contains a pointer to an entry in the page table entry (pte) array, an operating system data structure that stores virtual-to-physical address translations. if a tlb miss occurs, the operating system loads the untranslated data from the pte into the tlb to handle the software error. the xcontext register is used by the xtlb refill exception handler to load tlb entries in 64-bit addressing mode. the xcontext register duplicates some of the information provided in the badvaddr register, and puts it in a form useful for the xtlb exception handler. this register is included solely for operating system use. the operating system sets the ptebase field in the register, as needed. figure 3-22. xcontext register 32 0 35 34 33 63 4 3 ptebase r badvpn2 0 ptebase: base address of the pte entry table. r: space type (00 user, 01 supervisor, 11 kernel). the setting of this field matches virtual address bits 63 and 62. badvpn2: the value (vpn2) obtained by halving the virtual page number of the most recent virtual address for which translation failed. 0: reserved for future use. write 0 in a write operation. when this field is read, 0 is read. the 29-bit badvpn2 field has bits 39 to 11 of the virtual address that caused the tlb miss; bit 10 is excluded because a single tlb entry maps to an even-odd page pair. for a 1 kb page size, this format may be used directly to address the pair-table of 8-byte ptes. when the page size is 4 kb or more, shifting or masking this value produces the appropriate pte reference address. chapter 3 cp0 registers user ? s manual u14272ej3v0um 87 3.2.19 parity error register (26) the parity error (perr) register is a readable/writable register. this register is defined to maintain software- compatibility with the v r 4100, and is not used in hardware because the v r 4181 has no parity. figure 3-23. parity error register 0 87 31 0 diagnostic diagnostic:8-bit self diagnostic field. 0: reserved for future use. write 0 in a write operation. when this field is read, 0 is read. 3.2.20 cache error register (27) the cache error register is a readable/writable register. this register is defined to maintain software-compatibility with the v r 4100, and is not used in hardware because the v r 4181 has no parity. figure 3-24. cache error register 31 0 0 0: reserved for future use. write 0 in a write operation. when this field is read, 0 is read. chapter 3 cp0 registers user ? s manual u14272ej3v0um 88 3.2.21 taglo (28) and taghi (29) registers the taglo and taghi registers are 32-bit read/write registers that hold the primary cache tag during cache initialization, cache diagnostics, or cache error processing. the tag registers are written by the cache and mtc0 instructions. the contents of these registers are undefined after a reset. figure 3-25. taglo register 31 10 9 8 7 6 0 ptaglo (a) when used with data cache vdw 0 31 10 9 8 0 ptaglo (b) when used with instruction cache v0 ptaglo: specifies physical address bits 31 to 10. v: valid bit d: dirty bit. however, this bit is defined only for the compatibility with the v r 4000 series processors, and does not indicate the status of cache memory in spite of its readability and writability. this bit cannot change the status of cache memory. w: writeback bit (set if cache line has been updated) 0: reserved for future use. write 0 in a write operation. when this field is read, 0 is read. figure 3-26. taghi register 31 0 0 0: reserved for future use. write 0 in a write operation. when this field is read, 0 is read. chapter 3 cp0 registers user ? s manual u14272ej3v0um 89 3.2.22 errorepc register (30) the error exception program counter (errorepc) register is similar to the epc register. it is used to store the program counter value at which the cold reset, soft reset, or nmi exception has been serviced. the read/write errorepc register contains the virtual address at which instruction processing can resume after servicing an error. the contents of this register change depending on whether execution of mips16 instructions is enabled or disabled. setting the mips16en pin after rtc reset specifies whether the execution of mips16 instructions is enabled or disabled. when the mips16 instruction execution is disabled, either of the following addresses is contained in the errorepc register: ? virtual address of the instruction that caused the exception ? virtual address of the immediately preceding branch or jump instruction, when the instruction associated with the error exception is in a branch delay slot, and the bd bit in the cause register is set to 1 when the mips16 instruction execution is enabled, either of the following addresses is contained in the errorepc register during a 32-bit instruction execution: ? virtual address of the instruction that caused the exception and isa mode at which an exception occurs ? virtual address of the immediately preceding branch or jump instruction and isa mode at which an exception occurs when the instruction associated with the error exception is in a branch delay slot, and the bd bit in the cause register is set to 1 when the 16-bit instruction is executed, either of the following addresses is contained in the errorepc register: ? virtual address of the instruction that caused the exception and isa mode at which an exception occurs ? virtual address of the immediately preceding jump instruction or extend instruction and isa mode at which an exception occurs when the instruction associated with the error exception is in a branch delay slot of the jump instruction or is the instruction following the extend instruction, and the bd bit in the cause register is set to 1 the contents of the errorepc register do not change when the erl bit of the status register is set to 1. this prevents the processor when other exceptions occur from overwriting the address of the instruction in this register that causes an error exception. the errorepc register never indicates the address of the instruction in a branch delay slot. chapter 3 cp0 registers user ? s manual u14272ej3v0um 90 figure 3-27. errorepc register (when mips16 isa is disabled) (a) 32-bit mode 0 31 errorepc (b) 64-bit mode 0 63 errorepc errorepc: virtual restart address after cold reset, soft reset, or nmi exception. figure 3-28. errorepc register (when mips16 isa is enabled) (a) 32-bit mode 10 31 errorepc erim errorepc: bits 31 to 1 of virtual restart address after cold reset, soft reset, or nmi exception. erim: isa mode at which an error exception occurs (1 mips16 isa, 0 mips iii isa). (b) 64-bit mode 10 63 errorepc erim errorepc: bits 63 to 1 of virtual restart address after cold reset, soft reset, or nmi exception. erim: isa mode at which an error exception occurs (1 mips16 isa, 0 mips iii isa). user?s manual u14272ej3v0um 91 chapter 4 memory management system 4.1 overview the v r 4181 provides a memory management unit (mmu) which uses a translation lookaside buffer (tlb) to translate virtual addresses into physical addresses. virtual addresses are translated into physical addresses using an on-chip tlb. the on-chip tlb is a full- associative memory that holds 32 entries, which provide mapping to 32 odd/even page pairs for one entry. the tlb is accessed through the cp0 registers. note that the virtual address space includes areas that are translated to physical addresses without using a tlb, and areas where the use of cache memory can be selected. the v r 4181 has three operating modes: user, supervisor, and kernel; the manner in which memory addresses are mapped depends on these operating modes. in addition, the v r 4181 supports the 32-bit and 64-bit addressing modes; the manner in which memory addresses are translated or mapped depends on these addressing modes. for details about the memory management system and virtual address space, refer to v r 4100 series architecture user?s manual . chapter 4 memory management system user?s manual u14272ej3v0um 92 4.2 physical address space using a 32-bit address, the processor physical address space encompasses 4 gb. the v r 4181 uses this 4 gb physical address space as shown in figure 4-1. figure 4-1. v r 4181 physical address space 0xffff ffff (mirror image of 0x0000 0000 to 0x1fff ffff area) rom space (including a boot rom) external system bus memory space (isa memory) internal isa i/o space 1 internal isa i/o space 2 rfu dram space mba bus i/o space rfu 0x1800 0000 0x17ff ffff 0x0c00 0000 0x0bff ffff 0x0b00 0000 0x0aff ffff 0x0d00 0000 0x0cff ffff 0x0a00 0000 0x09ff ffff 0x0400 0000 0x03ff ffff 0x0000 0000 0x1000 0000 0x0fff ffff 0x2000 0000 0x1fff ffff external system bus i/o space (isa i/o) 0x1400 0000 0x13ff ffff chapter 4 memory management system user ? s manual u14272ej3v0um 93 table 4-1. v r 4181 physical address space physical address space capacity (bytes) 0xffff ffff to 0x2000 0000 mirror image of 0x1fff ffff to 0x0000 0000 3.5 g 0x1fff ffff to 0x1800 0000 rom space 128 m 0x17ff ffff to 0x1400 0000 external system bus i/o space (isa i/o) 64 m 0x13ff ffff to 0x1000 0000 external system bus memory space (isa memory) 64 m 0x0fff ffff to 0x0d00 0000 space reserved for future use 48 m 0x0cff ffff to 0x0c00 0000 internal isa i/o space 1 16 m 0x0bff ffff to 0x0b00 0000 internal isa i/o space 2 16 m 0x0aff ffff to 0x0a00 0000 mba bus i/o space 16 m 0x09ff ffff to 0x0400 0000 space reserved for future use 96 m 0x03ff ffff to 0x0000 0000 dram (sdram) space 64 m 4.2.1 rom space the rom space mapping differs depending on the capacity of the rom being used. the rom capacity is set via the roms(1:0) bits in the bcucntreg1 register. the physical addresses of the rom space are listed below. table 4-2. rom address map physical address when using 32-mbit rom when using 64-mbit rom 0x1fff ffff to 0x1fc0 0000 bank 3 (romcs3#) bank 3 (romcs3#) 0x1fbf ffff to 0x1f80 0000 bank 2 (romcs2#) 0x1f7f ffff to 0x1f40 0000 bank 1 (romcs1#) bank 2 (romcs2#) 0x1f3f ffff to 0x1f00 0000 bank 0 (romcs0#) 0x1eff ffff to 0x1e80 0000 reserved for future use bank 1 (romcs1#) 0x1e7f ffff to 0x1e00 0000 bank 0 (romcs0#) 4.2.2 external system bus space the following two types of system bus space are available. external system bus i/o space this corresponds to the isa ? s i/o space. external system bus memory space this corresponds to the isa ? s memory space. chapter 4 memory management system user ? s manual u14272ej3v0um 94 4.2.3 internal i/o space the v r 4181 has three internal i/o spaces. each of these spaces is described below. table 4-3. internal i/o space 1 physical address internal i/o 0x0c00 001f to 0x0c00 0010 siu1 0x0c00 000f to 0x0c00 0000 siu2 table 4-4. internal i/o space 2 physical address internal i/o 0x0b00 09ff to 0x0b00 0900 csi 0x0b00 08ff to 0x0b00 0800 ecu 0x0b00 07ff to 0x0b00 0400 reserved for future use 0x0b00 03ff to 0x0b00 0300 giu 0x0b00 02ff to 0x0b00 02d0 reserved for future use 0x0b00 02cf to 0x0b00 02c0 isa bridge 0x0b00 02bf to 0x0b00 02a0 piu-2 0x0b00 029f to 0x0b00 0280 reserved for future use 0x0b00 027f to 0x0b00 0260 a/d test 0x0b00 025f to 0x0b00 0240 led 0x0b00 023f to 0x0b00 01e0 reserved for future use 0x0b00 01df to 0x0b00 01c0 rtc-2 0x0b00 01bf to 0x0b00 01a0 reserved for future use 0x0b00 019f to 0x0b00 0180 kiu 0x0b00 017f to 0x0b00 0160 aiu 0x0b00 015f to 0x0b00 0140 reserved for future use 0x0b00 013f to 0x0b00 0120 piu-1 0x0b00 011f to 0x0b00 0100 reserved for future use 0x0b00 00ff to 0x0b00 00e0 dsu 0x0b00 00df to 0x0b00 00c0 rtc-1 0x0b00 00bf to 0x0b00 00a0 pmu 0x0b00 009f to 0x0b00 0080 icu-3 0x0b00 007f to 0x0b00 0000 reserved for future use chapter 4 memory management system user ? s manual u14272ej3v0um 95 table 4-5. mba bus i/o space physical address internal i/o 0x0a00 06ff to 0x0a00 0600 dcu-2 0x0a00 05ff to 0x0a00 0500 reserved for future use 0x0a00 04ff to 0x0a00 0400 lcd controller 0x0a00 03ff to 0x0a00 0300 memory controller 0x0a00 02ff to 0x0a00 0220 reserved for future use 0x0a00 021f to 0x0a00 0200 icu-2 0x0a00 01ff to 0x0a00 00a0 reserved for future use 0x0a00 009f to 0x0a00 0080 icu-1 0x0a00 007f to 0x0a00 0050 reserved for future use 0x0a00 004f to 0x0a00 0020 dcu-1 0x0a00 001f to 0x0a00 0000 mba host bridge 4.2.4 dram space the dram space differs depending on the capacity of the dram being used. the dram capacity is set via the b1config(1:0) bits in the memcfg_reg register. the physical addresses of the dram space are listed below. table 4-6. dram address map physical address when using 16-mbit dram when using 64-mbit dram 0x00ff ffff to 0x0080 0000 reserved for future use bank 1 (sdcs1#/ras1#) 0x007f ffff to 0x0040 0000 bank 0 (sdcs0#/ras0#) 0x003f ffff to 0x0020 0000 bank 1 (sdcs1#/ras1#) 0x001f ffff to 0x0000 0000 bank 0 (sdcs0#/ras0#) user?s manual u14272ej3v0um 96 chapter 5 initialization interface this chapter describes the reset signal descriptions and types, signal- and timing-related dependence, and the initialization sequence during each mode that can be selected by the user. a detailed description of the operation during and after a reset and its relationships to the power modes are also provided in chapter 10 power management unit (pmu) . remark # that follows signal names indicates active low. 5.1 reset function there are five ways to reset the v r 4181. each is summarized below. chapter 5 initialization interface user?s manual u14272ej3v0um 97 5.1.1 rtc reset during power-on, set the rtcrst# pin as active. after waiting about 600 ms for the 32.768 khz oscillator to begin oscillating when the power supply is stable at 3.0 v or above, setting the rtcrst# pin as inactive causes the rtc unit to begin counting. then, the states of the mips16en and clksel(2:0) pins are read after one rtc cycle. next, the v r 4181 asserts the poweron pin and checks the state of the battinh/battint# signal. if it is at high level, the v r 4181 asserts the mpower pin and activates the external agent?s dc/dc converter. after the stabilization time period (about 350 ms) of the dc/dc converter, the v r 4181 begins pll oscillation and starts all clocks (a period of about 16 ms following the start of pll oscillation is required for stabilization of pll oscillation). an rtc reset does not save any of the status information and it completely initializes the processor?s internal state. since the dram is not switched to self refresh mode, the contents of dram after an rtc reset are not at all guaranteed. after a reset, the processor becomes the system bus master, which executes a cold reset exception sequence and begins to access the reset exception vectors in the rom space. since only part of the internal status is reset when a reset occurs in the v r 4181, the processor should be completely initialized by software (see 5.4 notes on initialization ). after power-on, the processor?s pin statuses are undefined since the rtcrst# is asserted, until the 32.768 khz clock oscillator starts oscillation. the pin statuses after oscillation starts are described in chapter 2 pin functions in this document. figure 5-1. rtc reset l 16masterclock note reset# (internal) coldreset# (internal) mpower (output) undefined power (input) rtcrst# (input) rtc (internal, 32.768 khz) 16 ms > 600 ms pll (internal) > 32 ms poweron (output) 350 ms stable oscillation stable oscillation undefined note masterclock is the basic clock used in the cpu core. its frequency is one forth of tclock frequency. chapter 5 initialization interface user ? s manual u14272ej3v0um 98 5.1.2 rstsw reset after the rstsw# pin becomes active and then becomes inactive 100 s later, the v r 4181 starts pll oscillation and starts all clocks (a period of about 16 ms following the start of pll oscillation is required for stabilization of pll oscillation). an rstsw reset basically initializes the entire internal state except for the rtc timer, the giu, and the pmu. the v r 4181 has function to preserve dram data during rstsw reset. for detail, refer to chapter 10 power management unit (pmu) . after a reset, the processor becomes the system bus master, which executes a cold reset exception sequence and begins to access the reset exception vectors in the rom space. since only part of the internal status is reset when a reset occurs in the v r 4181, the processor should be completely initialized by software (see 5.4 notes on initialization ). figure 5-2. rstsw reset l 16masterclock note reset# (internal) coldreset# (internal) mpower (output) power (input) rstsw# (input) 16 ms pll (internal) > 3rtc h stable oscillation stable oscillation undefined stable oscillation rtc (internal, 32.768 khz) note masterclock is the basic clock used in the cpu core. its frequency is one forth of tclock frequency. chapter 5 initialization interface user ? s manual u14272ej3v0um 99 5.1.3 deadman?s switch reset after the deadman ? s switch unit is enabled, if the deadman ? s switch is not cleared within the specified time period, the v r 4181 immediately enters to reset status. setting and clearing of the deadman ? s switch is performed by software. a deadman ? s switch reset initializes the entire internal state except for the rtc timer, the giu, and the pmu. since the dram is not switched to self-refresh mode, the contents of dram after a deadman ? s switch reset are not at all guaranteed. after a reset, the processor becomes the system bus master, which executes a cold reset exception sequence and begins to access the reset vectors in the rom space. since only part of the internal status is reset when a reset occurs in the v r 4181, the processor should be completely initialized by software (see 5.4 notes on initialization ). figure 5-3. deadman?s switch reset l 16masterclock note reset# (internal) coldreset# (internal) mpower (output) power (input) rstsw# (input) rtc (internal, 32.768 khz) 16 ms pll (internal) h stable oscillation stable oscillation undefined stable oscillation h note masterclock is the basic clock used in the cpu core. its frequency is one forth of tclock frequency. chapter 5 initialization interface user ? s manual u14272ej3v0um 100 5.1.4 software shutdown when the software executes the hibernate instruction, the v r 4181 sets the mpower pin as inactive, then enters reset status. recovery from reset status occurs when the power pin or dcd# signal is asserted or when an unmasked wake-up interrupt request is occurred. a reset by software shutdown initializes the entire internal state except for the rtc timer, the giu, and the pmu. after a reset, the processor becomes the system bus master, which executes a cold reset exception sequence and begins to access the reset vectors in the rom space. since only part of the internal status is reset when a reset occurs in the v r 4181, the processor should be completely initialized by software (see 5.4 notes on initialization ). cauiton the v r 4181 does not set the dram to self-refresh mode at the transition to hibernate mode from fullspeed mode. to preserve dram data, software must set the dram to self-refresh mode. for details, refer to chapter 10 power management unit (pmu). figure 5-4. software shutdown 16masterclock note2 reset# (internal) coldreset# (internal) mpower (output) power (input) rtc (internal, 32.768 khz) 16 ms pll (internal) > 32 ms poweron (output) note1 stable oscillation undefined stopped stable oscillation notes 1. wait time for activation. it can be changed by setting the pmuwaitreg register. 2. masterclock is the basic clock used in the cpu core. its frequency is one forth of tclock frequency. chapter 5 initialization interface user ? s manual u14272ej3v0um 101 5.1.5 haltimer shutdown after an rtc reset or rstsw reset is canceled, if the haltimer is not canceled (the haltimerrst bit of the pmucntreg register is not set) by software within about four seconds, the v r 4181 enters reset status. recovery from reset status occurs when the power pin is asserted or when a elapsedtime interrupt request occurs. a reset by haltimer initializes the entire internal state except for the rtc timer, the giu, and the pmu. after a reset, the processor becomes the system bus master, which executes a cold reset exception sequence and begins to access the reset vectors in the rom space. since only part of the internal status is reset when a reset occurs in the v r 4181, the processor should be completely initialized by software (see 5.4 notes on initialization ). caution the v r 4181 does not sets the dram to self-refresh mode by haltimer shutdown. therefore, the contents of dram after a haltimer shutdown are not at all guaranteed. figure 5-5. haltimer shutdown 16masterclock note2 reset# (internal) coldreset# (internal) mpower (output) power (input) rtc (internal, 32.768 khz) 16 ms pll (internal) > 32 ms poweron (output) note1 undefined stopped stable oscillation about 4 s stable oscillation notes 1. wait time for activation. it can be changed by setting the pmuwaitreg register. 2. masterclock is the basic clock used in the cpu core. its frequency is one forth of tclock frequency. chapter 5 initialization interface user ? s manual u14272ej3v0um 102 5.2 power-on sequence the factors that cause the v r 4181 to switch from hibernate mode or shutdown mode to fullspeed mode are called activation factors. there are five activation factors: assertion of the power pin, the dcd1# pin or the gpio(15:0) pins, or activation of the elapsedtime or compactflash interrupt request. when an activation factor occurs, the v r 4181 asserts the poweron pin to notify to external agents that the v r 4181 is ready for power-on. three rtc clock cycles after the poweron pin is asserted, the v r 4181 checks the state of the battinh/battint# pin. if the battinh/battint# pin ? s state is low, the poweron pin is deasserted one rtc clock after the battinh/battint# pin check is completed, then the v r 4181 is not activated. if the battinh/battint# pin ? s state is high, the poweron pin is deasserted and the mpower pin is asserted three rtc clocks after the battinh/battint# pin check is completed, then the v r 4181 is activated. figure 5-6 shows a timing chart of v r 4181 activation and figure 5-7 shows a timing chart of when activation fails due to the battinh/battint# pin ? s ? low ? state. remark while the mpower pin is inactive, 2.5 v power supply of the v r 4181 (vdd_logic, vdd_pll) is not needed. in order to reduce leak current, it is recommended to turn on/off the 2.5 v power supply of the v r 4181 according to mpower pin state. figure 5-6. v r 4181 activation sequence (when activation is ok) reset# (internal) coldreset# (internal) mpower (output) battinh/battint# (input) rtc (internal, 32.768 khz) activation of cpu pll (internal) check battinh/battint# pin poweron (output) undefined stopped stable oscillation detection of activation factor chapter 5 initialization interface user ? s manual u14272ej3v0um 103 figure 5-7. v r 4181 activation sequence (when activation is ng) reset# (internal) coldreset# (internal) mpower (output) battinh/battint# (input) rtc (internal, 32.768 khz) cpu not activated pll (internal) check battinh/battint# pin poweron (output) h detection of activation factor l l l chapter 5 initialization interface user ? s manual u14272ej3v0um 104 5.3 reset of cpu core this section describes the reset sequence of the v r 4110 cpu core. 5.3.1 cold reset in the v r 4181, a cold reset sequence is executed in the cpu core in the following cases: ? rtc reset ? rstsw reset ? deadman ? s switch reset ? software shutdown ? haltimer shutdown ? battinh shutdown (shutdown according to battery state) a cold reset completely initializes the cpu core, except for the following register bits. ? the ts and sr bits of the status register are cleared to 0. ? the erl and bev bits of the status register are set to 1. ? the upper limit value (31) is set in the random register. ? the wired register is initialized to 0. ? the count register is initialized to 0. ? bits 31 to 28 of the config register are set to 0 and bits 22 to 3 to 0x04800; the other bits are undefined. ? the values of the other registers are undefined. once power to the processor is established, the coldreset# (internal) and the reset# (internal) signals are asserted and a cold reset is started. after approximately 2 ms assertion, the coldreset# signal is deasserted synchronously with the rising edge of masterout (internal). then the reset# signal is deasserted synchronously with the rising edge of masterout, and the cold reset is completed. upon reset, the cpu core becomes bus master and drives the sysad bus (internal). after reset# is deasserted, the cpu core branches to the reset exception vector and begins executing the reset exception code. figure 5-8. cold reset reset# (internal) coldreset# (internal) masterclock note (internal) v dd tclock (internal) masterout (internal) undefined undefined note masterclock is the basic clock used in the cpu core. its frequency is one forth of tclock frequency. chapter 5 initialization interface user ? s manual u14272ej3v0um 105 5.3.2 soft reset caution soft reset is not supported in the current v r 4181. a soft reset initializes the cpu core without affecting the output clocks; in other words, a soft reset is a logical reset. in a soft reset, the cpu core retains as much state information as possible; all state information except for the following is retained: ? the ts bit of the status register is cleared to 0. ? the sr, erl and bev bits of the status register are set to 1. ? the ip7 bit of the cause register is cleared to 0. ? any interrupts generated on the sysad bus are cleared. ? nmi is cleared. ? the config register is initialized. a soft reset is started by assertion of the reset# signal, and is completed at the deassertion of the reset# signal synchronized with the rising edge of masterout. in general, data in the cpu core is preserved for debugging purpose. upon reset, the cpu core becomes bus master and drives the sysad bus (internal). after reset# is deasserted, the cpu core branches to the reset exception vector and begins executing the reset exception code. figure 5-9. soft reset reset# (internal) masterclock note (internal) v dd tclock (internal) masterout (internal) h note masterclock is the basic clock used in the cpu core. its frequency is one forth of tclock frequency. chapter 5 initialization interface user ? s manual u14272ej3v0um 106 5.4 notes on initialization this section explains the case in which manipulation by software is necessary after the v r 4181 has been reset. when a cold reset sequence is executed, the reset exception vector is accessed. perform manipulation described here by using the software (handler) for reset exceptions located at the reset exception vector. 5.4.1 cpu core (1) coprocessor 0 be sure to initialize at least the following internal registers of the coprocessor 0 (cp0) after the rtc reset, rstsw reset, or deadman ? s switch reset has been cleared, or the v r 4181 has returned from the hibernate mode. ? config register ? status register ? watchlo register (2) cache tag the contents of the tag ram of the cache are undefined immediately after a voltage has been applied to the 2.5 v power supply when the rtc reset or deadman ? s switch reset has been cleared, or when the v r 4181 has returned from the hibernate mode. before accessing an address at which the cache can be used, therefore, be sure to initialize the contents of the tag ram of both the instruction cache and data cache. use the taglo register in cp0 to initialize the tags. 5.4.2 internal peripheral units (1) haltimer set the haltimerrst bit of the pmucntreg register in the pmu to 1 within 4 seconds after clearing the rtc reset or rstsw reset. this resets the haltimer. (2) memory controller before accessing the dram space, be sure to initialize the registers in the memory controller. especially when sdram is used, initialize sdram by executing the procedure described in 6.5.2 memcfg_reg (0x0a00 0304) . a function to operate sdclk only when sdram is accessed, for example, is not valid unless a mode setting command is issued to sdram by using the memcfg_reg register. (3) clock supply to peripheral units the clock is not supplied in the default status to the peripheral units such as csi, aiu, piu, siu1, and siu2, and the a/d and d/a converters. to start using these units and converters, supply the necessary clock to them by setting the cmuclkmsk register in the mba host bridge. if these units are not used or they have finished being used, mask the clock supply by setting the cmuclkmsk register. (4) alternate-function pins the function of an alternate-function pin and the i/o direction of the gpio pins are selected by the registers in the giu. be sure to set these registers in accordance with the unit or the function of the pin to be used. exercise care in setting the registers so that signals do not conflict on the board or that a signal whose level is required does not go into a high-impedance state. chapter 5 initialization interface user ? s manual u14272ej3v0um 107 5.4.3 returning from power mode for initialization after the v r 4181 has returned from the hibernate mode or suspend mode, refer to 10.6 dram interface control . user?s manual u14272ej3v0um 108 chapter 6 bus control 6.1 mba host bridge the mba (modular bus architecture) host bridge is an interface between the cpu core and the mba bus and operates as an external agent to the cpu core. it handles all requests from the cpu core if it is provided proper resources. the mba host bridge can decode the entire physical address space to start appropriate bus accesses such as mba requests, mba - isa protocols, or external rom accesses through the peripheral bus. it also has functions as a host bridge to implement proper cycle timings and bus transaction protocols. figure 6-1. v r 4181 internal bus structure mba bus isa bridge internal isa peripherals mba peripherals (lcd, dma) memoty controller v r 4110 cpu core mba host bridge internal isa bus sysad bus chapter 6 bus control user ? s manual u14272ej3v0um 109 6.1.1 mba host bridge rom and register address space physical address type device 0x1fff ffff to 0x1800 0000 memory (range) rom 0x0a00 0014 to 0x0a00 0000 i/o (range) bus control registers 0x0a00 0080 i/o interrupt register 0x0a00 008c i/o interrupt register 0x0a00 0098 i/o interrupt register 0x0a00 009a i/o interrupt register 0x0a00 0200 i/o interrupt register 0x0a00 0206 i/o interrupt register in addition to the decoding of above addresses, the host bridge generates mba select signals if other mba masters intend to access the above devices. the host bridge responds to the above addresses only upon a cpu access. for any other addresses the host bridge initiates an mba cycle to access an appropriate resources. 6.1.2 mba modules address space (1) memory controller physical address type device 0x03ff ffff to 0x0000 0000 memory (range) dram 0x0a00 03ff to 0x0a00 0300 i/o (range) control registers the mba memory controller is selected when the above address ranges are accessed. (2) dma controller physical address type device 0x0a00 0048 to 0x0a00 0020 i/o (range) control registers 1 0x0a00 06ff to 0x0a00 0600 i/o (range) control registers 2 the mba dma controller is selected when the above i/o ranges are accessed. (3) lcd module (lcd control unit) physical address type device 0x0a00 05ff to 0x0a00 0400 i/o (range) control registers the lcd module is selected when the above i/o range is accessed. chapter 6 bus control user ? s manual u14272ej3v0um 110 (4) isa bridge physical address type device 0x17ff ffff to 0x1400 0000 i/o (64m, range) external isa bus (i/o) 0x13ff ffff to 0x1000 0000 memory (64m, range) external isa bus (memory) 0x0bff ffff to 0x0b00 0000 i/o (16m, range) isa internal i/o 1 0x0cff ffff to 0x0c00 0000 i/o (16m, range ) isa internal i/o 2 the isa bridge is selected when the above address ranges are accessed. 6.2 bus control registers external rom accesses and supply of clocks to several internal units are controlled by the bus control registers listed below. table 6-1. bus control registers physical address r/w register symbol function 0x0a00 0000 r/w bcucntreg1 bcu control register 1 0x0a00 0004 r/w cmuclkmsk clock mask register 0x0a00 000c r/w bcuspeedreg bcu access time parameters register 0x0a00 0010 r/w bcurfcntreg bcu refresh control register 0x0a00 0014 r revidreg revision id register 0x0a00 0018 r clkspeedreg clock speed register caution since these registers are powered by 2.5 v power supply, the contents of these registers are cleared after hibernate mode. chapter 6 bus control user ? s manual u14272ej3v0um 111 6.2.1 bcucntreg1 (0x0a00 0000) bit 151413121110 9 8 name roms1 roms0 reserved reserved reserved reserved reserved reserved r/w r/wr/wrrrrrr at reset10000000 bit 76543210 name reserved reserved reserved romwen0 reserved rtype1 rtype0 rstout r/w r r r r/w r r/w r/w r/w at reset00000000 bit name function 15, 14 roms(1:0) defines rom size to be used (for all banks) 00 : reserved 01 : 32 mbit 10 : 64 mbit 11 : reserved 13 to 5 reserved 0 is returned when read 4 romwen0 enables flash memory write (for all banks). write strobe can be generated when this bit is set to 1. 0 : disabled 1 : enabled 3 reserved 0 is returned when read 2, 1 rtype(1:0) rom type (for all banks) 00 : ordinary rom 01 : flash memory 10 : page rom 11 : reserved 0 rstout reset# output control. this bit does not affect gpio21/reset# pin ? s state when this pin is not defined as reset# output. 0 : reset# is active (low level) 1 : reset# is inactive (high level) this register is used to set rom type and capacity of rom bank 0, 1, 2 and 3. caution when writing to flash memory, be sure to set rtype(1:0) bits to 01 in addition to a setting of romwen0 bit to 1. remark when a rom type other than flash memory is selected (rtype(1:0) bits are set to other than 01), the operation of the v r 4181 is undefined if a write to the rom space is performed. chapter 6 bus control user ? s manual u14272ej3v0um 112 6.2.2 cmuclkmsk (0x0a00 0004) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr at reset00000000 bit 76543210 name reserved mskcsu pclk mskaiu pclk mskpiu pclk mskadu pclk msksiu 18m mskadu 18m reserved r/w r r/w r/w r/w r/w r/w r/w r/w at reset00000000 bit name function 15 to 7 reserved 0 is returned when read 6 mskcsupclk supply/mask clocked serial interface (csi) peripheral clock (pclk) 0 : mask 1 : supply 5 mskaiupclk supply/mask audio interface (aiu) peripheral clock (pclk) 0 : mask 1 : supply 4 mskpiupclk supply/mask touch panel interface (piu) peripheral clock (pclk) 0 : mask 1 : supply 3 mskadupclk supply/mask a/d converter and d/a converter peripheral clock (pclk) 0 : mask 1 : supply 2 msksiu18m supply/mask serial interface 1 and 2 (siu1/siu2) 18.432 mhz clock 0 : mask 1 : supply 1 mskadu18m supply/mask a/d converter and d/a converter 18.432 mhz clock 0 : mask 1 : supply 0 reserved write 0 when write. 0 is returned when read. this register is used to mask the clocks that are supplied to csi, aiu, piu, siu1, and siu2. chapter 6 bus control user ? s manual u14272ej3v0um 113 6.2.3 bcuspeedreg (0x0a00 000c) bit 151413121110 9 8 name reserved wprom2 wprom1 wprom0 reserved reserved reserved reserved r/w rr/wr/wr/wrrrr at reset01110000 bit 76543210 name reserved reserved reserved reserved wroma3 wroma2 wroma1 wroma0 r/w r r r r r/w r/w r/w r/w at reset00001111 bit name function 15 reserved 0 is returned when read 14 to 12 wprom(2:0) page rom access speed 000 : 1.5 tclock 001 : 2.5 tclock 010 : 3.5 tclock 011 : 4.5 tclock 100 : 5.5 tclock 101 : 6.5 tclock 110 : 7.5 tclock 111 : 8.5 tclock 11 to 4 reserved 0 is returned when read 3 to 0 wroma(3:0) rom access speed 0000 : 1.5 tclock 0001 : 2.5 tclock 0010 : 3.5 tclock 0011 : 4.5 tclock 0100 : 5.5 tclock 0101 : 6.5 tclock 0110 : 7.5 tclock 0111 : 8.5 tclock 1000 : 9.5 tclock 1001 : 10.5 tclock 1010 : 11.5 tclock 1011 : 12.5 tclock 1100 : 13.5 tclock 1101 : 14.5 tclock 1110 : 15.5 tclock 1111 : 16.5 tclock this register is used to set rom access parameter of bank 0, 1, 2, and 3. about the relationship between these bits and rom cycles, refer to figure 6-2. rom read cycle and access parameters . remark the maximum burst number when using a pagerom is 8 halfwords (i.e. 128 bits; 1 word = 32 bits). chapter 6 bus control user ? s manual u14272ej3v0um 114 figure 6-2. rom read cycle and access parameters (a) ordinary rom cycle tclock (internal) add(21:0) (output) memrd# (output) data(15:0) (read) romcs(3:0)# (output) wroma(3:0) valid valid (b) pagerom cycle wroma(3:0) add(2:0) (output) tclock (internal) add(21:3) (output) data(15:0) (read) romcs(3:0)# (output) wprom(2:0) valid valid valid valid valid remarks 1. romcs(2:0)# signals are alternated with general-purpose i/o signals and are defined as general-purpose inputs after rtc reset. set gpmd2reg and gpmd3reg registers in the giu to use them as romcs(2:0)#. 2. a circle in the figure indicates the sampling timing. chapter 6 bus control user ? s manual u14272ej3v0um 115 6.2.4 bcurfcntreg (0x0a00 0010) bit 151413121110 9 8 name reserved reserved brf13 brf12 brf11 brf10 brf9 brf8 r/w r r r/w r/w r/w r/w r/w r/w at reset00011111 bit 76543210 name brf7 brf6 brf5 brf4 brf3 brf2 brf1 brf0 r/w r/w r/w r/w r/w r/w r/w r/w r/w at reset11111111 bit name function 15, 14 reserved 0 is returned when read 13 to 0 brf(13:0) these bits select the dram refresh rate that is based on the tclock. the refresh rate is obtained by following expression. refresh rate = brf(13:0) x tclock period for example, to select a 15.6 s refresh rate with a 50 mhz tclock: brf(13:0) = 15600 (ns) / 20 (ns) = 0x30c remarks 1. when the iordy signal does not become high level though the dram refresh rate has elapsed during the external isa memory or i/o cycles, a dram refresh cycle may be lost. 2. refresh timing is generated from detecting match between values of the internal up counter and bcurfcntreg register. therefore, when the bcurfcntreg register value is changed smaller than current value, and if the internal counter value is larger than the new bcurfcntreg register value, the next cbr refresh timing is at next match after the counter rounds over. chapter 6 bus control user ? s manual u14272ej3v0um 116 6.2.5 revidreg (0x0a00 0014) bit 151413121110 9 8 name rid3 rid2 rid1 rid0 mjrev3 mjrev2 mjrev1 mjrev0 r/w rrrrrrrr bit 76543210 name reserved reserved reserved reserved mnrev3 mnrev2 mnrev1 mnrev0 r/w rrrrrrrr bit name function 15 to 12 rid(3:0) processor revision id (read only) 11 to 8 mjrev(3:0) major revision id number (read only) 7 to 4 reserved 0 is returned when read 3 to 0 mnrev(3:0) minor revision id (read only) this register is used to indicate the revision of the v r 4181. the relationship between the values and the revision of the v r 4181 is as follows. v r 4181 revision rid(3:0) mjrev(3:0) minrev(3:0) 1.0 0x0 0x0 0x0 1.1 0x0 0x0 0x1 1.2 0x0 0x0 0x2 1.3 0x0 0x0 0x2 even if the cpu core or the peripheral unit has been changed, there is no guarantee that revidreg register will be reflected, or that the changes to the revision number necessarily reflect real changes of the cpu core or the peripheral unit. for this reason, software should not rely on the revision number in revidreg register to characterize the units. caution values of this register bits differ depending on the delivery date. chapter 6 bus control user ? s manual u14272ej3v0um 117 6.2.6 clkspeedreg (0x0a00 0018) bit 151413121110 9 8 name div2 div3 div4 reserved reserved reserved reserved reserved r/w rrrrrrrr bit 76543210 name reserved reserved reserved clksp4 clksp3 clksp2 clksp1 clksp0 r/w rrrrrrrr bit name function 15 to 13 div(2:4) value used to calculate the tclock, mba clock, and sdclk operating frequency 12 to 5 reserved 0 is returned when read 4 to 0 clksp(4:0) value used to calculate the cpu core operating clock (pclock) frequency the following expression is used to calculate the pclock and tclock frequency: (1) cpu core clock (pclock) pclock = (18.432 mhz / clksp(4:0)) x 64 (2) peripheral clock (tclock) div(2:4) ratio mode 111 tclock = pclock / 1 div1 mode 011 tclock = pclock / 2 div2 mode 101 tclock = pclock / 3 div3 mode others reserved ? remark pclock frequency is decided by clksel(2:0) pin statuses during rtc reset. tclock frequency is always a half of pclock frequency (div2 mode) immediately after rtc reset. software can change tclock div mode by setting the pmudivreg register (0x0b00 00ac). a change becomes valid when the v r 4181 restores from the hibernate mode after setting the pmudivreg register. chapter 6 bus control user ? s manual u14272ej3v0um 118 6.3 rom interface the v r 4181 supports three rom modes, ordinary rom, pagerom, and flash memory. the mode setting is made via the bcucntreg1 register ? s rtype(1:0) bits and romwen0 bit. access speed setting in ordinary rom or pagerom mode is made via the bcuspeedreg register. remark the v r 4181 supports only 16-bit access for external rom devices. 6.3.1 external rom devices memory mapping physical address 32 mbit rom 64 mbit rom 0x1fff ffff to 0x1fc0 0000 bank 3 (romcs3#) bank 3 (romcs3#) 0x1fbf ffff to 0x1f80 0000 bank 2 (romcs2#) 0x1f7f ffff to 0x1f40 0000 bank 1 (romcs1#) bank 2 (romcs2#) 0x1f3f ffff to 0x1f00 0000 bank 0 (romcs0#) 0x1eff ffff to 0x1e80 0000 reserved bank 1 (romcs1#) 0x1e7f ffff to 0x1e00 0000 reserved bank 0 (romcs0#) bank 3 contains boot vector and has a dedicated pin for chip select (romcs3#). chip select pins for bank 2, 1, and 0, romcs(2:0)#, are alternated with general-purpose i/o signals and are defined as general-purpose inputs after rtc reset. set gpmd2reg and gpmd3reg registers in the giu to use them as romcs(2:0)#. chapter 6 bus control user ? s manual u14272ej3v0um 119 6.3.2 connection to external rom (x 16) devices the add(21:0) pins are connected to the address line add(21:0) inside the v r 4181 during dram accesses. however, during rom or flash memory accesses, they are connected to the address line add(22:1) inside the v r 4181. this allows providing a greater address space capacity for rom or flash memory. rom address pin 32 mbit rom (2 mbits x 16) 64 mbit rom (4 mbits x 16) v r 4181 pin cpu core physical address line v r 4181 pin cpu core physical address a21 add21 adr22 a20 add20 adr21 add20 adr21 a19 add19 adr20 add19 adr20 a18 add18 adr19 add18 adr19 a17 add17 adr18 add17 adr18 a16 add16 adr17 add16 adr17 a15 add15 adr16 add15 adr16 a14 add14 adr15 add14 adr15 a13 add13 adr14 add13 adr14 a12 add12 adr13 add12 adr13 a11 add11 adr12 add11 adr12 a10 add10 adr11 add10 adr11 a9 add9 adr10 add9 adr10 a8 add8 adr9 add8 adr9 a7 add7 adr8 add7 adr8 a6 add6 adr7 add6 adr7 a5 add5 adr6 add5 adr6 a4 add4 adr5 add4 adr5 a3 add3 adr4 add3 adr4 a2 add2 adr3 add2 adr3 a1 add1 adr2 add1 adr2 a0 add0 adr1 add0 adr1 chapter 6 bus control user ? s manual u14272ej3v0um 120 6.3.3 example of rom connection (1) 32 mbit ordinary rom a(20:0) d(15:0) a(20:0) romcs0# rom bank1 rom bank0 add(20:0) romcs2# romcs1# data(15:0) rom bank3 rom bank2 romcs3# a(20:0) a(20:0) d(15:0) d(15:0) d(15:0) (2) 64 mbit ordinary rom a(21:0) d(15:0) a(21:0) romcs0# rom bank1 rom bank0 add(21:0) romcs2# romcs1# data(15:0) rom bank3 rom bank2 romcs3# a(21:0) a(21:0) d(15:0) d(15:0) d(15:0) chapter 6 bus control user ? s manual u14272ej3v0um 121 (3) 32 mbit pagerom remark the maximum burst number when using a pagerom is 8 halfwords (i.e. 128 bits; 1 word = 32 bits). ce ce ce ce a(1: ? 1) dw/w# a(19:2) romcs0# a(19:2) d(15:0) a(19:2) page rom bank1 page rom bank0 add(20:3) romcs2# romcs1# data(15:0) page rom bank3 page rom bank2 romcs3# a(19:2) a(1: ? 1) d(15:0) d(15:0) d(15:0) a(1: ? 1) a(1: ? 1) dw/w# dw/w# dw/w# add(2:0) chapter 6 bus control user ? s manual u14272ej3v0um 122 (4) 64 mbit pagerom remark the maximum burst number when using a pagerom is 8 halfwords (i.e. 128 bits; 1 word = 32 bits). ce ce ce ce a(1: ? 1) dw/w# a(20:2) romcs0# a(20:2) d(15:0) a(20:2) page rom bank1 page rom bank0 add(21:3) romcs2# romcs1# data(15:0) page rom bank3 page rom bank2 romcs3# a(20:2) a(1: ? 1) d(15:0) d(15:0) d(15:0) a(1: ? 1) a(1: ? 1) dw/w# dw/w# dw/w# add(2:0) chapter 6 bus control user ? s manual u14272ej3v0um 123 (5) 32 mbit flash memory (when using intel tm dd28f032) rdy/bsy# rdy/bsy# rdy/bsy# romcs2# romcs0# romcs3# ce0 ce2 a(20:1) oe we memrd# memwr# romcs1# a(20:1) d(15:0) a(20:1) flash memory bank1 flash memory bank0 add(19:0) data(15:0) flash memory bank3 flash memory bank2 a(20:1) ce0 d(15:0) d(15:0) d(15:0) oe we ce0 oe we ce0 oe we ce1 ce2 ce1 ce2 ce1 ce2 ce1 rdy/bsy# flash ready note add20 note there is no corresponding pin in the v r 4181. use one of the gpio pins for this function. remark use one of the gpio pins in the v r 4181 to control on/off of v pp (program/erase supply voltage). chapter 6 bus control user ? s manual u14272ej3v0um 124 (6) 64 mbit flash memory (when using intel strataflash tm 28f640j5) sts sts sts ce0 ce2 a(21:0) oe we memrd# memwr# romcs0# a(21:0) d(15:0) a(21:0) flash memory bank1 flash memory bank0 add(21:0) romcs2# romcs1# data(15:0) flash memory bank3 flash memory bank2 romcs3# a(21:0) ce0 d(15:0) d(15:0) d(15:0) oe we ce0 oe we ce0 oe we ce1 ce2 ce1 ce2 ce1 ce2 ce1 sts flash status note note there is no corresponding pin in the v r 4181. using one of the gpio pins for this function. remark using one of the gpio pins in the v r 4181 to control on/off of v pp (program/erase supply voltage). chapter 6 bus control user ? s manual u14272ej3v0um 125 6.3.4 external rom cycles the following timing diagrams illustrate the external rom cycles depending on the settings in the bus control register and bus speed control register. (1) ordinary rom read cycle figure 6-3. ordinary rom read cycle (wroma(3:0) = 0101) tclock (internal) add(21:0) (output) memrd# (output) data(15:0) (read) romcs(3:0)# (output) wroma(3:0) valid valid remark a circle in the figure indicates the sampling timing. chapter 6 bus control user ? s manual u14272ej3v0um 126 (2) pagerom read cycle figure 6-4. pagerom read cycle (wroma(3:0) = 0011, wprom(2:0) = 001) adr0 tclock (internal) add(21:0) (output) memrd# (output) data(15:0) (read) romcs(3:0)# (output) wroma(3:0) l wprom(2:0) adr1 adr2 adr3 adr4 adr5 adr6 adr7 data1 data4 data3 data2 data6 data5 data7 data0 wprom(2:0) wprom(2:0) wprom(2:0) wprom(2:0) wprom(2:0) wprom(2:0) remark a circle in the figure indicates the sampling timing. chapter 6 bus control user ? s manual u14272ej3v0um 127 (3) flash memory read cycle figure 6-5. flash memory read cycle (rtype(1:0) = 01, wroma(3:0) = 0101) tclock (internal) add(21:0) (output) memrd# (output) data(15:0) (read) romcs(3:0)# (output) wroma(3:0) valid valid remark a circle in the figure indicates the sampling timing. (4) flash memory write cycle figure 6-6. flash memory write cycle (rtype(1:0) = 01, wroma(3:0) = 0100) tclock (internal) add(21:0) (output) memwr# (output) data(15:0) (write) romcs(3:0)# (output) wroma(3:0) valid valid chapter 6 bus control user ? s manual u14272ej3v0um 128 6.4 dram interface the v r 4181 supports 16 mbit or 64 mbit dram (edo dram or sdram). the dram size, type, and access speed is set via the memory controller ? s registers. 6.4.1 edo dram configuration figure 6-7. external edo dram configuration we# edo dram bank1 a(12:0) d(15:0) ras# ucas# lcas# memwr# we# ras0# ucas# add(12:0) data(15:0) v r 4181 edo dram bank0 a(12:0) d(15:0) ras# ras1# oe# lcas# ucas# lcas# oe# figure 6-7 illustrates an example when connecting devices of 4 mbits x 16. addresses when connecting devices of 16 mbits or 64 mbits are mapped as follows. dram bank physical address (16 mbits) physical address (64 mbits) bank 0 0x001f ffff to 0x0000 0000 0x007f ffff to 0x0000 0000 bank 1 0x003f ffff to 0x0020 0000 0x00ff ffff to 0x0080 0000 remark 64 mbit edo drams of other than 13 rows and 9 columns cannot be used with the v r 4181. chapter 6 bus control user ? s manual u14272ej3v0um 129 6.4.2 mixed memory mode (edo dram only) the memcfg_reg register provides two bits each for bank 0 and bank 1 to set types of drams to be used. this allows the two banks to be configured with different types of drams, for example, bank 0 can be mapped on 64 mbit devices and bank 1 on 16 mbit devices, to optimize the cost of the total memory required. table 6-2. v r 4181 edo dram capacity bank 0 bank 1 total dram capacity 16 mbits 0 2 mb 16 mbits 16 mbits 4 mb 64 mbits 0 8 mb 16 mbits 64 mbits 10 mb 64 mbits 16 mbits 10 mb 64 mbits 64 mbits 16 mb 6.4.3 edo dram timing parameters the following table shows examples of edo dram timing parameters when using edo drams with access time of 60 ns. these parameters are set in edomcytreg register. tclock frequency ras to cas delay cas pulse width cas precharge ras precharge ras pulse width self refresh ras precharge 66 mhz 3 tclock 1 tclock 1 tclock 3 tclock 3 tclock 8 tclock 50 mhz 2 tclock 1 tclock 1 tclock 2 tclock 3 tclock 6 tclock 33 mhz 2 tclock 1/2 tclock 1/2 tclock 2 tclock 2 tclock 4 tclock 25 mhz 2 tclock 1/2 tclock 1/2 tclock 1 tclock 2 tclock 3 tclock chapter 6 bus control user ? s manual u14272ej3v0um 130 6.4.4 sdram configuration figure 6-8. sdram configuration ldqm ldqm ldqm d(15:0) cs# udqm we# a(13:0) cke clk ras# cas# sdcs0# data(15:0) d(15:0) cs# udqm udqm sdram bank1 memwr# we# sdclk sdras# add(13:0) clken v r 4181 sdram bank0 a(13:0) cke clk sdcs1# cas# ras# cas# figure 6-8 illustrates an example when connecting devices of 4 mbits x 16. remark the sdrams supported by the v r 4181 are as follows. capacity configuration address pins bank address 16 mbits 512 kbits x 16 x 2 banks a(10:0) a11 64 mbits 2 mbits x 16 x 2 banks a(12:0) a13 64 mbits 1 mbits x 16 x 4 banks a(11:0) a(13:12) chapter 6 bus control user ? s manual u14272ej3v0um 131 6.5 memory controller register set table 6-3. memory controller registers physical address r/w register symbol function 0x0a00 0300 r/w edomcytreg edo dram timing register 0x0a00 0304 r/w memcfg_reg memory configuration register 0x0a00 0308 r/w mode_reg sdram mode register 0x0a00 030c r/w sdtimingreg sdram timing register caution since these registers are powered by 2.5 v power supply, the contents of these registers are cleared after hibernate mode. 6.5.1 edomcytreg (0x0a00 0300) (1/2) bit 151413121110 9 8 name reserved reserved reserved srefrpre2 srefrpre1 srefrpre0 caspre1 caspre0 r/w r r r r/w r/w r/w r/w r/w at reset00000000 bit 76543210 name rcasdly1 rcasdly0 tcas1 tcas0 trp1 trp0 tras1 tras0 r/w r/w r/w r/w r/w r/w r/w r/w r/w at reset00000000 bit name function 15 to 13 reserved 0 is returned when read 12 to 10 srefrpre(2:0) self refresh ras precharge time 000 : 3 tclock 001 : 4 tclock 010 : 6 tclock 011 : 8 tclock 100 : 11 tclock others : reserved 9, 8 caspre(1:0) cas precharge time 00 : 1/2 tclock 01 : 1 tclock 10 : 2 tclock 11 : reserved 7, 6 rcasdly(1:0) ras to cas delay time 00 : 2 tclock 01 : 3 tclock 10 : 5 tclock 11 : 6 tclock chapter 6 bus control user ? s manual u14272ej3v0um 132 (2/2) bit name function 5, 4 tcas(1:0) cas pulse width 00 : 1/2 tclock 01 : 1 tclock 10 : 2 tclock 11 : reserved 3, 2 trp(1:0) ras precharge time 00 : 1 tclock 01 : 2 tclock 10 : 3 tclock 11 : 4 tclock 1, 0 tras(1:0) ras pulse width 00 : 2 tclock 01 : 3 tclock 10 : 5 tclock 11 : 6 tclock this register is used to set edo dram timing parameters. software must set these parameters suitable before using dram. remark do not set tcas = 1/2 tclock and caspre = 1 tclock, or tcas = 1 tclock and caspre = 1/2 tclock at the same time. chapter 6 bus control user ? s manual u14272ej3v0um 133 6.5.2 memcfg_reg (0x0a00 0304) (1/2) bit 151413121110 9 8 name init reserved reserved reserved b1config1 b1config0 reserved bstreftype r/w r/w r r r r/w r/w r r/w at reset00000000 bit 76543210 name bstrefr edoasym reserved reserved reserved b0config1 b0config0 edo/ sdram r/w r/w r/w r r r r/w r/w r/w at reset00000000 bit name function 15 init this bit is for sdram only. when software writes 1 to this bit, the memory controller issues a sdram mode set command. after the sdram mode is set, hardware automatically resets this bit to 0. when edo dram is used, this bit must not be set to 1. 14 to 12 reserved 0 is returned when read 11, 10 b1config(1:0) bank 1 capacity 00 : bank 1 is not installed 01 : 16 mbits 10 : 64 mbits 11 : reserved 9 reserved 0 is returned when read 8 bstreftype burst refresh type. this bit determines the number of cbr burst refresh cycles executed before entering and exiting self-refresh mode. 0 : 8 rows refreshed 1 : all rows refreshed 7 bstrefr burst refresh enable. this bit enables or disables burst cbr refresh cycles when entering or exiting self-refresh mode. 0 : disable cbr burst refresh 1 : enable cbr burst refresh burst and distributive cbr refresh are mixed if this bit is set to 1. for some kind of drams, mix use of burst and distributive cbr refresh may not be allowed. 6 edoasym edo dram configuration 0 : asymmetrical 16 mbit edo dram : 12 rows by 8 columns 64 mbit edo dram : 13 rows by 9 columns 1 : symmetrical 16 mbit edo dram : 10 rows by 10 columns 64 mbit edo dram : setting prohibited chapter 6 bus control user ? s manual u14272ej3v0um 134 (2/2) bit name function 5 to 3 reserved 0 is returned when read 2, 1 b0config(1:0) bank 0 capacity 00 : bank 0 is not installed 01 : 16 mbit 10 : 64 mbit 11 : reserved 0 edo/sdram dram type 0 : edo dram 1 : sdram this register is used to set dram type (capacity, type, organization, etc.) of bank 0 and bank 1. caution when using sdrams, set the init bit to 1 to initialize sdrams before accessing them after an rtc reset or rstsw reset is canceled or after the v r 4181 restores from the hibernate mode. an initialization of sdrams must be executed until the v r 4181 issues the first cbr auto refresh cycle. remark during the 64 mbit sdram mode register write, a13 of the address bus is at high level. on the other hand, during the 16 mbit sdram mode register write, a13 is at low level. in order to initialize 64-mbit sdram correctly, software must execute the following sequence. <1> set b0config(1:0) and b1config(1:0) bits of memcfg_reg register to 01 <2> set mode_reg register to appropriate value (0x00n7, n can be any value) <3> initialize sdram by setting init bit of memcfg_reg register <4> set b0config(1:0) and b1config(1:0) bits of memcfg_reg register to 10 chapter 6 bus control user ? s manual u14272ej3v0um 135 6.5.3 mode_reg (0x0a00 0308) bit 151413121110 9 8 name reserved reserved reserved reserved 0 0 br-sw te-ven1 r/w r r r r r/w r/w r/w r/w at reset00000000 bit 76543210 name te-ven2 ltmode2 ltmode1 ltmode0 wt bl2 bl1 bl0 r/w r/w r/w r/w r/w r/w r/w r/w r/w at reset00000000 bit name function 15 to 12 reserved 0 is returned when read 11, 10 0 these bits should be always written to 00. 9 br-sw burst read - single write this bit should be always written to 0. 8, 7 te-ven(1:2) these two bits define a jedec test cycle and vendor specific cycles. these bits should be always written to 00. 6 to 4 ltmode(2:0) cas latency mode note 010 : 2 clocks 011 : 3 clocks others : reserved 3 wt wrap type for the burst cycles. this bit s hould be always written to 0. 0 : sequential (default) 2 to 0 bl(2:0) burst length. these bits should be always written to 111. 111 : full page (when wt = 0 only. setting prohibited when wt = 1) note the cas latency mode must be set according to the operation frequency of the sdclk (sdram clock). this register is used to set the value output to add(13:0) pins during the sdram mode register setting cycle. this register should be written before the init bit of memcfg_reg register is set to 1. chapter 6 bus control user ? s manual u14272ej3v0um 136 6.5.4 sdtimingreg (0x0a00 030c) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrr/wr/w at reset00000000 bit 76543210 name tras1 tras0 trc1 trc0 trp1 trp0 trcd1 trcd0 r/w r/w r/w r/w r/w r/w r/w r/w r/w at reset00000000 bit name function 15 to 10 reserved 0 is returned when read 9 reserved write 0 when write. note 8 reserved write 1 when write. note 7, 6 tras(1:0) tras in clock cycles 00 : 3 sdclk (for 25 mhz sdclk) 01 : 5 sdclk (for 66, 50, or 33 mhz sdclk) others : prohibited 5, 4 trc(1:0) trc in clock cycles 00 : 4 sdclk (for 25 mhz sdclk) 01 : 7 sdclk (for 66, 50, or 33 mhz sdclk) others : prohibited 3, 2 trp(1:0) trp in clock cycles 00 : 1 sdclk (for 25 mhz sdclk) 01 : prohibited 10 : 3 sdclk (for 66, 50, or 33 mhz sdclk) 11 : prohibited 1, 0 trcd(1:0) trcd in clock cycles 00 : 1 sdclk (for 25 mhz sdclk) 01 : 2 sdclk (for 66, 50, or 33 mhz sdclk) others : prohibited note bits 9 and 8 must be set to 01 before using sdram. especially, be sure to set 1 to bit 8 since its default value is 0. when these bits are not 01, the v r 4181 may not work correctly. this register is used to set sdram timing parameters. software must set this register suitable before using sdram. chapter 6 bus control user ? s manual u14272ej3v0um 137 6.6 isa bridge the v r 4181 has an external bus used for rom, flash memory, dram, and i/o. this bus ? s operation emulates an isa bus at accesses to external memory and i/o spaces. the v r 4181 also uses an isa bus internally for the slow, embedded peripherals. among the pins used for accesses in the external isa bus, ube#, iocs16#, iordy, iowr#, and iord# share the pins with gpio(20:16), as well as memcs16# with loclk. to use these pins as an external isa bus interface, make settings in the giu in advance. 6.7 isa bridge register set the following registers provide configuration and control of the isa bridge. table 6-4. isa bridge registers physical address r/w register symbol function 0x0b00 02c0 r/w isabrgctl isa bridge control register 0x0b00 02c2 r/w isabrgsts isa bridge status register 0x0b00 02c4 r/w xisactl external isa control register chapter 6 bus control user ? s manual u14272ej3v0um 138 6.7.1 isabrgctl (0x0b00 02c0) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit 76543210 name reserved reserved reserved reserved reserved reserved pclkdiv1 pclkdiv0 r/w r r r r r r r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit name function 15 to 2 reserved 0 is returned when read 1, 0 pclkdiv(1:0) pclk (peripheral clock) divisor rate selection. these bits select the operating frequency of pclk. 00 : tclock / 8 01 : tclock / 4 10 : tclock / 2 11 : tclock / 1 this register is used to set the pclk divisor rate. pclk is a clock for internal isa peripherals, and its frequency must be set to between 18.432 mhz and 33 mhz. chapter 6 bus control user ? s manual u14272ej3v0um 139 6.7.2 isabrgsts (0x0b00 02c2) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit 76543210 name reserved reserved reserved reserved reserved reserved reserved idle r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit name function 15 to 1 reserved 0 is returned when read 0 idle isa bridge status 0 : isa bridge is busy 1 : isa bridge is idle this register shows the isa bridge operation status. chapter 6 bus control user ? s manual u14272ej3v0um 140 6.7.3 xisactl (0x0b00 02c4) (1/2) bit 151413121110 9 8 name reserved reserved reserved reserved reserved extresult intresult exbuffen r/w r r r r r r/w r/w r/w rtcrst 0 0 0 0 0 1 0 1 other resets00000101 bit 76543210 name memws1 memws0 iows1 iows0 reserved reserved sclkdiv1 sclkdiv0 r/w r/w r/w r/w r/w r r r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit name function 15 to 11 reserved 0 is returned when read 10 extresult external isa result cycle enable 0 : disabled. the mba bus arbiter waits until an external isa read is finished. 1 : enabled. the mba bus arbiter issues a result cycle to the isa bri dge after finishing an external isa cycle and obtains results of the read. normally, set 1 to this bit. 9 intresult internal isa result cycle enable 0 : disabled. the mba bus arbiter waits until an internal isa read is finished. 1 : enabled. the mba bus arbiter issues a result cycle to the isa bri dge after finishing an internal isa cycle and obtains results of the read. normally, set 1 to this bit. 8 exbuffen external buffer enable 0 : enable external buffer control with sysdir and sysen# pins 1 : disable external buffer control with sysdir and sysen# pins (sysen# and sysdir pins are both forced to low level) 7, 6 memws(1:0) external isa memory wait states (read/write strobe width) 00 : 1.5 sysclk cycles 01 : 2.5 sysclk cycles 10 : 3.5 sysclk cycles 11 : 4.5 sysclk cycles 5, 4 iows(1:0) external isa i/o wait states (read/write strobe width) 00 : 1.5 sysclk cycles 01 : 2.5 sysclk cycles 10 : 3.5 sysclk cycles 11 : 4.5 sysclk cycles chapter 6 bus control user ? s manual u14272ej3v0um 141 (2/2) bit name function 3, 2 reserved 0 is returned when read 1, 0 sclkdiv(1:0) sysclk (external isa bus clock) divisor rate selection 00 : pclk / 2 01 : pclk / 3 10 : pclk / 6 11 : pclk / 8 this register is used to set the external isa configurations. sysclk is an operation clock for the external isa bus, and is output only when an external isa cycle is generated. user?s manual u14272ej3v0um 142 chapter 7 dma control unit (dcu) 7.1 general the dma control unit (dcu) controls four channels of dma transfer. two of them are allocated for the aiu (microphone and speaker), though the remaining two are reserved for future use. the microphone channel performs the i/o-to-memory transfers from the a/d converter included in the aiu to memory. the speaker channel performs the memory-to-i/o transfers from memory to the d/a converter included in the aiu. each dma channel supports both the primary and the secondary memory buffers. the source1/source2 or destination1/destination2 address registers for the associated channel determine the starting address of each memory buffer. the sizes of memory buffers are determined in the associated record length registers. the dcu uses the primary and secondary dma buffers alternately when transferring. for example, during the first dma transfer following either hardware or software reset of the dcu, the transfer starts using the primary dma buffer. if the total number of dma transfers through the primary dma buffer reaches the value set in the associated record length register, the next dma transfer is performed using the secondary dma buffer. software must keep track of which buffer contains valid dma data. software may configure any of the dma channels to operate in one of two modes; auto-stop or auto-load. when a channel is configured to operate in auto-stop mode, the dcu terminates dma transfers after the number of transfers specified by the record length register and automatically resets the dma mask bit for that channel. once the mask bit is automatically reset, the dcu ignores all subsequent dma requests for this channel. to resume dma transfers in this mode, software must again unmask dma transfers for this channel. once software unmasks dma requests, the dcu resumes dma transfers utilizing the secondary memory buffer. when a channel is configured to operate in auto-load mode, the dcu does not terminate dma transfers after the number of dma transfers specified by the record length register. instead, the dcu automatically switchs to the secondary dma buffer and continues servicing dma requests. in either mode, auto-stop or auto-load, the dcu always alternates the dma buffer to be used between the primary and secondary buffers. software must keep track of the total number of transfers and assure the appropriate dma buffer is loaded with new dma data before starting another dma transfer. the dcu can be programmed to generate an eop (end of process) interrupt request independent of auto-stop or auto-load mode. an eop interrupt request is generated once the number of dma transfers has reached to the value specified by the record length register. chapter 7 dma control unit (dcu) user?s manual u14272ej3v0um 143 priority of each dma channel is fixed. the channel priority is as follows. 1. aiu microphone channel 2. aiu speaker channel dcu runs at the mba bus clock (tclock) frequency. remark the dcu contains a 32-bit temporary storage register for each dma channel. for memory-to-i/o transfers, the dcu performs a 32-bit memory read from dram and stores the read data into the temporary storage register. the dcu then transfers data from this register to the target i/o device. for a 16-bit device such as the speaker channel, the dcu performs two i/o writes to the d/a converter for each memory read. during dma transfers, all dcu registers are write-protected if valid data is present in the temporary storage registers. because of this, to start dma transfers, software must read the register that is written immediately after the write to confirm that the register has been correctly set. chapter 7 dma control unit (dcu) user?s manual u14272ej3v0um 144 7.2 dcu registers table 7-1. dcu registers physical address r/w register symbol function 0x0a00 0020 r/w micdest1reg1 microphone destination 1 address register 1 0x0a00 0022 r/w micdest1reg2 microphone destination 1 address register 2 0x0a00 0024 r/w micdest2reg1 microphone destination 2 address register 1 0x0a00 0026 r/w micdest2reg2 microphone destination 2 address register 2 0x0a00 0028 r/w spkrsrc1reg1 speaker source 1 address register 1 0x0a00 002a r/w spkrsrc1reg2 speaker source 1 address register 2 0x0a00 002c r/w spkrsrc2reg1 speaker source 2 address register 1 0x0a00 002e r/w spkrsrc2reg2 speaker source 2 address register 2 0x0a00 0040 r/w dmarstreg dma reset register 0x0a00 0046 r/w aiudmamskreg audio dma mask register 0x0a00 0600 to 0x0a00 0654 r/w ? reserved. write 0 when write. 0 is returned after a read. 0x0a00 0658 r/w micrclenreg microphone record length register 0x0a00 065a r/w spkrclenreg speaker record length register 0x0a00 065c r/w ? reserved. write 0 when write. 0 is returned after a read. 0x0a00 065e r/w micdmacfgreg microphone dma configuration register 0x0a00 0660 r/w spkdmacfgreg speaker dma configuration register 0x0a00 0662 r/w dmaitrqreg dma interrupt request register 0x0a00 0664 r/w dmactlreg dma control register 0x0a00 0666 r/w dmaitmkreg dma interrupt mask register chapter 7 dma control unit (dcu) user?s manual u14272ej3v0um 145 7.2.1 microphone destination 1 address registers (1) micdest1reg1 (0x0a00 0020) bit 151413121110 9 8 name md1a15 md1a14 md1a13 md1a12 md1a11 md1a10 md1a9 md1a8 r/w r/w r/w r/w r/w r/w r/w r/w r/w at reset00000000 bit 76543210 name md1a7 md1a6 md1a5 md1a4 md1a3 md1a2 md1a1 md1a0 r/w r/w r/w r/w r/w r/w r/w r/w r/w at reset00000000 bit name function 15 to 0 md1a(15:0) lower 16 bits (a(15:0)) of dma destination 1 address for microphone (2) micdest1reg2 (0x0a00 0022) bit 151413121110 9 8 name md1a31 md1a30 md1a29 md1a28 md1a27 md1a26 md1a25 md1a24 r/w r/w r/w r/w r/w r/w r/w r/w r/w at reset00000000 bit 76543210 name md1a23 md1a22 md1a21 md1a20 md1a19 md1a18 md1a17 md1a16 r/w r/w r/w r/w r/w r/w r/w r/w r/w at reset00000000 bit name function 15 to 0 md1a(31:16) upper 16 bits (a(31:16)) of dma destination 1 address for microphone these two registers specify the destination memory address of the primary dma buffer for the microphone channel. chapter 7 dma control unit (dcu) user?s manual u14272ej3v0um 146 7.2.2 microphone destination 2 address registers (1) micdest2reg1 (0x0a00 0024) bit 151413121110 9 8 name md2a15 md2a14 md2a13 md2a12 md2a11 md2a10 md2a9 md2a8 r/w r/w r/w r/w r/w r/w r/w r/w r/w at reset00000000 bit 76543210 name md2a7 md2a6 md2a5 md2a4 md2a3 md2a2 md2a1 md2a0 r/w r/w r/w r/w r/w r/w r/w r/w r/w at reset00000000 bit name function 15 to 0 md2a(15:0) lower 16 bits (a(15:0)) of dma destination 2 address for microphone (2) micdest2reg2 (0x0a00 0026) bit 151413121110 9 8 name md2a31 md2a30 md2a29 md2a28 md2a27 md2a26 md2a25 md2a24 r/w r/w r/w r/w r/w r/w r/w r/w r/w at reset00000000 bit 76543210 name md2a23 md2a22 md2a21 md2a20 md2a19 md2a18 md2a17 md2a16 r/w r/w r/w r/w r/w r/w r/w r/w r/w at reset00000000 bit name function 15 to 0 md2a(31:16) upper 16 bits (a(31:16)) of dma destination 2 address for microphone these two registers specify the destination memory address of the secondary dma buffer for the microphone channel. chapter 7 dma control unit (dcu) user?s manual u14272ej3v0um 147 7.2.3 speaker source 1 address registers (1) spkrsrc1reg1 (0x0a00 0028) bit 151413121110 9 8 name ss1a15 ss1a14 ss1a13 ss1a12 ss1a11 ss1a10 ss1a9 ss1a8 r/w r/w r/w r/w r/w r/w r/w r/w r/w at reset00000000 bit 76543210 name ss1a7 ss1a6 ss1a5 ss1a4 ss1a3 ss1a2 ss1a1 ss1a0 r/w r/w r/w r/w r/w r/w r/w r/w r/w at reset00000000 bit name function 15 to 0 ss1a(15:0) lower 16 bits (a(15:0)) of dma source 1 address for speaker (2) spkrsrc1reg2 (0x0a00 002a) bit 151413121110 9 8 name ss1a31 ss1a30 ss1a29 ss1a28 ss1a27 ss1a26 ss1a25 ss1a24 r/w r/w r/w r/w r/w r/w r/w r/w r/w at reset00000000 bit 76543210 name ss1a23 ss1a22 ss1a21 ss1a20 ss1a9 ss1a18 ss1a17 ss1a16 r/w r/w r/w r/w r/w r/w r/w r/w r/w at reset00000000 bit name function 15 to 0 ss1a(31:16) upper 16 bits (a(31:16)) of dma source 1 address for speaker these two registers specify the source memory address of the primary dma buffer for the speaker channel. chapter 7 dma control unit (dcu) user?s manual u14272ej3v0um 148 7.2.4 speaker source 2 address registers (1) spkrsrc2reg1 (0x0a00 002c) bit 151413121110 9 8 name ss2a15 ss2a14 ss2a13 ss2a12 ss2a11 ss2a10 ss2a9 ss2a8 r/w r/w r/w r/w r/w r/w r/w r/w r/w at reset00000000 bit 76543210 name ss2a7 ss2a6 ss2a5 ss2a4 ss2a3 ss2a2 ss2a1 ss2a0 r/w r/w r/w r/w r/w r/w r/w r/w r/w at reset00000000 bit name function 15 to 0 ss2a(15:0) lower 16 bits (a(15:0)) of dma source 2 address for speaker (2) spkrsrc2reg2 (0x0a00 002e) bit 151413121110 9 8 name ss2a31 ss2a30 ss2a29 ss2a28 ss2a27 ss2a26 ss2a25 ss2a24 r/w r/w r/w r/w r/w r/w r/w r/w r/w at reset00000000 bit 76543210 name ss2a23 ss2a22 ss2a21 ss2a20 ss2a9 ss2a18 ss2a17 ss2a16 r/w r/w r/w r/w r/w r/w r/w r/w r/w at reset00000000 bit name function 15 to 0 ss2a(31:16) upper 16 bits (a(31:16)) of dma source 2 address for speaker these two registers specify the source memory address of the secondary dma buffer for the speaker channel. chapter 7 dma control unit (dcu) user?s manual u14272ej3v0um 149 7.2.5 dmarstreg (0x0a00 0040) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr at reset00000000 bit 76543210 name reserved reserved reserved reserved reserved reserved reserved dmarst r/w rrrrrrrr/w at reset00000001 bit name function 15 to 1 reserved 0 is returned after a read. 0 dmarst resets dma functions 0 : resets dma channels 1 : normal operation when dmarst bit is written to zero, all active dma transfers are immediately terminated and the dcu enters in the reset state. while dmarst bit is 0, all dma requests become pending until this bit is set to 1. 7.2.6 aiudmamskreg (0x0a00 0046) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr at reset00000000 bit 76543210 name reserved reserved reserved reserved micmsk spkmsk reserved reserved r/w r r r r r/w r/w r r at reset00000000 bit name function 15 to 4 reserved 0 is returned after a read. 3 micmsk masks dma for micr ophone (audio input) channel 0 : microphone channel disabled 1 : microphone channel enabled 2 spkmsk masks dma for s peaker (audio output) channel 0 : speaker channel disabled 1 : speaker channel enabled 1, 0 reserved 0 is returned after a read. chapter 7 dma control unit (dcu) user?s manual u14272ej3v0um 150 7.2.7 micrclenreg (0x0a00 0658) bit 151413121110 9 8 name micrl15 micrl14 micrl13 micrl12 micrl11 micrl10 micrl9 micrl8 r/w r/w r/w r/w r/w r/w r/w r/w r/w at reset11111111 bit 76543210 name micrl7 micrl6 micrl5 micrl4 micrl3 micrl2 micrl1 micrl0 r/w r/w r/w r/w r/w r/w r/w r/w r/w at reset11111111 bit name function 15 to 0 micrl(15:0) dma record length for microphone. micrl0 bit must be written to zero. this register defines the number of 16-bit words to be transferred during dma operation in the microphone channel. 7.2.8 spkrclenreg (0x0a00 065a) bit 151413121110 9 8 name spkrl15 spkrl14 spkrl13 spkrl12 spkrl11 spkrl10 spkrl9 spkrl8 r/w r/w r/w r/w r/w r/w r/w r/w r/w at reset11111111 bit 76543210 name spkrl7 spkrl6 spkrl5 spkrl4 spkrl3 spkrl2 spkrl1 spkrl0 r/w r/w r/w r/w r/w r/w r/w r/w r/w at reset11111111 bit name function 15 to 0 spkrl(15:0) dma record length for speaker. spkrl0 bit must be written to zero. this register defines the number of 16-bit words to be transferred during dma operation in the speaker channel. chapter 7 dma control unit (dcu) user?s manual u14272ej3v0um 151 7.2.9 micdmacfgreg (0x0a00 065e) bit 151413121110 9 8 name reserved micdsize1 micdsize0 micsrctype micdestype reserved reserved micload r/w rrrrrrrr/w at reset00110000 bit 76543210 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr at reset00000000 bit name function 15 reserved 0 is returned after a read. 14, 13 micdsize(1:0) indicates microphone channel data size 01 : 16 bits values other than above do not appear. 12 micsrctype indicates microphone channel source address type 1 : i/o 0 does not appear. 11 micdestype indicates microphone channel destination address type 0 : memory 1 does not appear. 10, 9 reserved 0 is returned after a read. 8 micload dma auto-stop/auto-load mode setting for microphone channel 0 : auto-stop 1 : auto-load when this bit is set to 1, the dcu automatically begins transferring data to the secondary buffer when the primary buffer is full. when this bit is set to 0, the dcu uses the primary buffer only. 7 to 0 reserved 0 is returned after a read. chapter 7 dma control unit (dcu) user?s manual u14272ej3v0um 152 7.2.10 spkdmacfgreg (0x0a00 0660) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr at reset00000000 bit 76543210 name reserved spkdsize1 spkdsize0 spksrctype spkdestype reserved reserved spkload r/w rrrrrrrr/w at reset00101000 bit name function 15 to 7 reserved 0 is returned after a read. 6, 5 spkdsize(1:0) indicates speaker channel data size 01 : 16 bits values other than above do not appear. 4 spksrctype indicates speaker channel source address type 0 : memory 1 does not appear. 3 spkdestype indicates speaker channel destination address type 1 : i/o 0 does not appear. 2, 1 reserved 0 is returned after a read. 0 spkload dma auto-stop/auto-load mode setting for speaker channel 0 : auto-stop 1 : auto-load when this bit is set to 1, the dcu automatically begins transferring data from the secondary buffer when the primary buffer is empty. when this bit is set to 0, the dcu uses the primary buffer only. chapter 7 dma control unit (dcu) user?s manual u14272ej3v0um 153 7.2.11 dmaitrqreg (0x0a00 0662) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr at reset00000000 bit 76543210 name reserved reserved spkeop miceop reserved reserved reserved reserved r/w r r r/w r/w r r/w r/w r at reset00000000 bit name function 15 to 6 reserved 0 is returned after a read. 5 spkeop speaker channel end of process (eop) interrupt status 0 : none 1 : speaker channel eop interrupt pending the interrupt request is cleared when this bit is written to 1. 4 miceop microphone channel eop interrupt status 0 : none 1 : microphone channel eop interrupt pending the interrupt request is cleared when this bit is written to 1. 3 reserved 0 is returned after a read. 2, 1 reserved write 0 when write. 0 is returned after a read. 0 reserved 0 is returned after a read. this register indicates interrupt status of each dma channel by end of process (eop). once an interrupt occurs, clear the interrupt request by writing a zero to the corresponding status bit in this register. chapter 7 dma control unit (dcu) user?s manual u14272ej3v0um 154 7.2.12 dmactlreg (0x0a00 0664) bit 151413121110 9 8 name spkcnt1 spkcnt0 miccnt1 miccnt0 reserved reserved reserved reserved r/w r/wr/wr/wr/wrrrr at reset00000000 bit 76543210 name reserved reserved reserved reserved reserved reserved reserved reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w at reset00000000 bit name function 15, 14 spkcnt(1:0) speaker channel source address count control 00 : increment 01 : decrement others : reserved 13, 12 miccnt(1:0) microphone channel destination address count control 00 : increment 01 : decrement others : reserved 11 to 8 reserved 0 is returned after a read. 7 to 0 reserved write 0 when write. 0 is returned after a read. chapter 7 dma control unit (dcu) user?s manual u14272ej3v0um 155 7.2.13 dmaitmkreg (0x0a00 0666) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr at reset00000000 bit 76543210 name reserved reserved spkeopmsk miceopmsk reserved reserved reserved reserved r/w r r r/w r/w r r/w r/w r at reset00000000 bit name function 15 to 6 reserved 0 is returned after a read. 5 spkeopmsk speaker channel end of process (eop) interrupt mask 0 : disable 1 : enable 4 miceopmsk microphone channel eop interrupt mask 0 : disable 1 : enable 3 reserved 0 is returned after a read. 2, 1 reserved write 0 when write. 0 is returned after a read. 0 reserved 0 is returned after a read. user?s manual u14272ej3v0um 156 chapter 8 clocked serial interface unit (csi) 8.1 overview the csi manages communication via a synchronous serial bus. the csi of the v r 4181 has the following key characteristics: ? slave-only synchronous serial interface ? able to transmit and receive data simultaneously ? supports fixed 8-bit character length ? supports burst lengths of 1 to 65535 bits ? continuous transfer mode for of peripherals supporting auto-scan ? programmable clock phase and clock polarity the csi interface shares pins with gpio signals as follows. when using the csi, set these pins to use as csi signals in the registers of the giu in advance. gpio pin csi signal definition gpio10 frm optional multifunction control input. in one mode, frm determines data direction (transmit or receive). in the other mode, frm enables (low level) or inhibits (high level) transmissions. gpio2 sck serial clock input (maximum frequency: 1.6 mhz) gpio1 so serial data output gpio0 si serial data input caution no clock is supplied to the csi in the initial state. when using the csi, set the mskcsupclk bit of the cmuclkmsk register in the mba host bridge to 1 in advance so that a clock is supplied. 8.2 operation of csi 8.2.1 transmit/receive operations transmit and receive operations are initiated by an external master to drive the serial clock, sck. the characteristics of the protocol are controlled by the csimode register, in particular by ckpol, ckmd, frmen, and frmmd bits. ckpol and ckmd bits control the relationship between data driven on so and si, and the phase of the serial clock input to sck. frmen and frmmd bits enable and control the frm input. chapter 8 clocked serial interface unit (csi) user?s manual u14272ej3v0um 157 8.2.2 sck phase and csi transfer timing the external master drives sck and si and samples data driven on so. the csi supports 4 basic operating modes of sck depending on the settings of ckpol and ckmd bits. these are illustrated in the following figure. figure 8-1. sck and si/so relationship (a) when ckmd bit = 0 sck (input) (when ckpol = 0) sck (input) (when ckpol = 1) so (output) si (input) undefined d7 d6 d0 d5 d4 d3 d2 d1 (b) when ckmd bit = 1 sck (input) (when ckpol = 0) sck (input) (when ckpol = 1) so (output) si (input) undefined d7 d6 d0 d5 d4 d3 d2 d1 caution when the ckmd bit is set to 1, the next byte data is output during the latter half of the cycle for the eighth bit of a transmit data. this figure illustrates csi cycles when the frm input is disabled (frmen bit = 0) or configured to provide direction control (frmen bit = 1 and frmmd bit = 0). when frmen bit = 1 and frmmd bit = 1, so is driven as high impedance during a high level input to frm. in addition, this figure illustrates the csi cycles when bit 7 of a data is transmitted or received first (i.e. when the lsbmsb bit of the csimode register = 0). chapter 8 clocked serial interface unit (csi) user ? s manual u14272ej3v0um 158 the four modes of sck are described below. (1) when ckmd bit = 0 and ckpol bit = 0 ? transmission the first transmit data bit is output before the first rising edge of sck. the second transmit data and those that follow are output synchronized with the falling edge of sck. therefore, the external master must sample the data synchronizing with the rising edge of sck. ? reception the external master must output the first data bit before the first rising edge of sck. the v r 4181 samples receive data synchronizing with the rising edge of sck. therefore, the external master must output data synchronizing with the falling edge of sck. (2) when ckmd bit = 0 and ckpol bit = 1 ? transmission the first transmit data bit is output before the first falling edge of sck. the second transmit data bit and those that follow are output synchronized with the rising edge of sck. therefore, the external master must sample the data synchronizing with the falling edge of sck. ? reception the external master must output the first data bit before the first falling edge of sck. the v r 4181 samples receive data synchronizing with the falling edge of sck. therefore, the external master must output data synchronizing with the rising edge of sck. (3) when ckmd bit = 1 and ckpol bit = 0 ? transmission the first transmit data bit is output synchronized with the first rising edge of sck. the second transmit data bit and those that follow are output synchronized with the rising edge of sck. therefore, the external master must sample the data synchronizing with the falling edge of sck. ? reception the v r 4181 samples receive data synchronizing with the falling edge of sck. therefore, the external master must output data synchronizing with the rising edge of sck. (4) when ckmd bit = 1 and ckpol bit = 1 ? transmission the first transmit data bit is output synchronized with the first falling edge of sck. the second transmit data bit and those that follow are output synchronized with the falling edge of sck. therefore, the external master must sample the data synchronizing with the rising edge of sck. ? reception the v r 4181 samples receive data synchronizing with the rising edge of sck. therefore, the external master must output data synchronizing with the falling edge of sck. chapter 8 clocked serial interface unit (csi) user ? s manual u14272ej3v0um 159 8.2.3 csi transfer types (1) burst mode burst mode is supported for both transmit and receive transfers. burst lengths for transmission and reception are independently programmable and can be set from 1 to 65535 bits. the transmit and receive shift registers are both 8-bit lengths. during burst mode, when the receive shift register goes ? full ? , the data is automatically transferred to the receive fifo. when the transmit shift register goes ? empty ? , it is automatically reloaded from the transmit fifo. once the burst length has been set and the burst transaction enabled, the csi behaves as follows: the csi begins tracking the number of bits transmitted and/or received. at the end of each bit transfer, the bit count is updated and compared to the corresponding burst length value (transmit and/or receive). if the number of bits transferred is equal to the burst length, the csi shift register is halted. if the transfer is a reception, the contents of the shift register will be copied to the receive fifo, a receive burst end interrupt request will be generated if unmasked, and additional activities on the sck input will be ignored. if the transfer is a transmission, a transmit burst end interrupt request will be generated if unmasked and additional sck cycles will cause an invalid data to be output on so. (2) continuous mode continuous mode transfers are always defined as 8-bit fixed length transfers. in continuous mode, software must control the flow of data between the v r 4181 and the external master. when continuous mode is enabled and the receive shift register goes ? full ? , the data is automatically transferred to the receive fifo. when the transmit shift register goes ? empty ? , it is automatically reloaded from the transmit fifo. chapter 8 clocked serial interface unit (csi) user ? s manual u14272ej3v0um 160 8.2.4 transmit and receive fifos the csi contains two 8-deep 16-bit fifos. one is for transmission and the other for reception. the transmit and receive shift registers access the fifos by 8 bits at a time. the cpu core accesses the fifos in either 8-bit or 16-bit units. the threshold of each fifo is independently programmable. for the transmit fifo, an interrupt request is generated to inform the cpu that 1, 2, or 4 16-bit words are empty in the fifo. for the receive fifo, an interrupt request is generated to inform the cpu core that 1, 2, or 4 16-bit words can be read from the fifo. the fifo control logic can also generate interrupt requests to signal an overrun condition for the receive fifo or an underrun condition for the transmit fifo. an overrun occurs when the receive shift register attempts to transfer data to a location in the fifo which has not be read by the cpu core. an underrun occurs when the transmit shift register attempts to load a value from the fifo which has not been updated by the cpu core. (1) overrun/underrun errors when an overrun error occurs, the receive fifo logic generates an overrun interrupt request if unmasked, and overwrites the next location in the fifo with the contents of the receive shift register. when an underrun error occurs, the transmit fifo logic generates an underrun interrupt request if unmasked, and reloads the transmit shift register with the contents of the next location in the fifo. the software must recover the data loss caused by the overrun or underrun error. 8.3 csi registers the csi provides the following registers: table 8-1. csi registers physical address r/w register symbol function 0x0b00 0900 r/w csimode csi mode register 0x0b00 0902 r csirxdata csi receive data register 0x0b00 0904 r/w csitxdata csi transmit data register 0x0b00 0906 r/w csilstat csi line status register 0x0b00 0908 r/w csiintmsk csi interrupt mask register 0x0b00 090a r/w csiintstat csi interrupt status register 0x0b00 090c r/w csitxblen csi transmit burst length register 0x0b00 090e r/w csirxblen csi receive burst length register chapter 8 clocked serial interface unit (csi) user ? s manual u14272ej3v0um 161 8.3.1 csimode (0x0b00 0900) (1/2) bit 151413121110 9 8 name frmen txen txbmd txclr reserved rxen rxbmd rxclr r/w r/w r/w r/w r/w r r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit 76543210 name frmmd ckpol ckmd reserved reserved reserved reserved lsbmsb r/w r/w r/w r/w r r r r r/w rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit name function 15 frmen csi frm enable 0 : disabled. frm signal input is ignored. 1 : enabled. mode is set by frmmd bit. 14 txen csi transmit enable 0 : disable 1 : enable remark when using the transmit function only, communication must be performed with the rxen bit = 0 and the rxclr bit = 1. 13 txbmd csi transmit burst mode 0 : continuous mode 1 : burst mode 12 txclr csi transmit buffer clear 0 : enable transmit shift register and fifo 1 : reset transmit shift register and fifo 11 reserved 0 is returned after read 10 rxen csi receive enable 0 : disable 1 : enable remark when using the receive function only, communication must be performed with the txen bit = 0 and the txclr bit = 1. 9 rxbmd csi receive burst mode 0 : continuous mode 1 : burst mode 8 rxclr csi receive buffer clear 0 : enable receive shift register and fifo 1 : reset receive shift register and fifo chapter 8 clocked serial interface unit (csi) user ? s manual u14272ej3v0um 162 (2/2) bit name function 7 frmmd frm mode 0 : frm controls transfer directions (receive when frm= 1, transmit when frm= 0) 1 : frm enables transfers (transmit/receive enabled when frm = 0) 6 ckpol csi clock polarity note 0 : sck is active high (1st transition is low to high) 1 : sck is active low (1st transition is high to low) 5ckmd csi clocking mode note 0 : character data is valid prior to the 1st transition of sck 1 : character data is valid at the 1st transition of sck 4 to 1 reserved 0 is returned after read 0 lsbmsb transmit/receive mode bit ordering 0 : bit 7 is the first bit transmitted or received (msb mode) 1 : bit 0 is the first bit transmitted or received (lsb mode) note the txclr and rxclr bits must be cleared after changing the ckpol or ckmd bit. the ckpol bit must be set as follows according to the state of sck when a communication is not performed: ? when sck is at low level during no communication ? ckpol bit = 0 ? when sck is at high level during no communication ? ckpol bit = 1 chapter 8 clocked serial interface unit (csi) user ? s manual u14272ej3v0um 163 8.3.2 csirxdata (0x0b00 0902) bit 151413121110 9 8 name rxd15 rxd14 rxd13 rxd12 rxd11 rxd10 rxd9 rxd8 r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit 76543210 name rxd7 rxd6 rxd5 rxd4 rxd3 rxd2 rxd1 rxd0 r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit name function 15 to 0 rxd(15:0) csi receive data. csi data received on the si pin is read through these data bits. 8.3.3 csitxdata (0x0b00 0904) bit 151413121110 9 8 name txd15 txd14 txd13 txd12 txd11 txd10 txd9 txd8 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit 76543210 name txd7 txd6 txd5 txd4 txd3 txd2 txd1 txd0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit name function 15 to 0 txd(15:0) csi transmit data. csi data written to these bits is transmitted on the so pin. chapter 8 clocked serial interface unit (csi) user ? s manual u14272ej3v0um 164 8.3.4 csilstat (0x0b00 0906) (1/2) bit 151413121110 9 8 name tfifot1 tfifot0 reserved reserved reserved txfifof txfifoe txbusy r/w r/wr/wrrrrrr rtcrst 0 0 0 0 0 0 1 0 other resets00000010 bit 76543210 name rfifot1 rfifot0 reserved frmdir reserved rxfifof rxfifoe rxbusy r/w r/wr/wrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit name function 15, 14 tfifot(1:0) csi transmit fifo threshold. these bits select the level at which the transmit fifo empty status is notified. 00 : 1 or more words are free in transmit fifo 01 : 2 or more words are free in transmit fifo 10 : 4 or more words are free in transmit fifo 11 : reserved 13 to 11 reserved 0 is returned after read 10 txfifof csi transmit fifo full status. this bit is set to 1 when the transmit fifo contains no free space. 0 : transmit fifo not full 1 : transmit fifo full 9 txfifoe csi transmit fifo empty status. this bit is set to 1 when the transmit fifo reaches to the empty level defined by tfifot bits. 0 : transmit fifo not empty 1 : transmit fifo empty 8 txbusy csi transmit shift register status 0 : idle 1 : character transmission in progress 7, 6 rfifot(1:0) csi receive fifo threshold. these bits select the level at which the receive fifo full status is notified. 00 : 1 or more words are valid in receive fifo 01 : 2 or more words are valid in receive fifo 10 : 4 or more words are valid in receive fifo 11 : reserved 5 reserved 0 is returned after read chapter 8 clocked serial interface unit (csi) user ? s manual u14272ej3v0um 165 (2/2) bit name function 4 frmdir frm input pin status 0 : low level (transmit direction) 1 : high level (receive direction) 3 reserved 0 is returned after read 2 rxfifof csi receive fifo full status. this bit is set to 1 when the receive fifo reaches to the full level defined by rfifot bits. 0 : receive fifo not full 1 : receive fifo full 1 rxfifoe csi receive fifo empty status. this bit is set to 1 when the receive fifo contains no valid data. 0 : receive fifo not empty 1 : receive fifo empty 0 rxbusy csi receive shift register status 0 : idle 1 : character reception in progress chapter 8 clocked serial interface unit (csi) user ? s manual u14272ej3v0um 166 8.3.5 csiintmsk (0x0b00 0908) bit 151413121110 9 8 name reserved reserved reserved reserved mundrn mt xbend mtxfifoe mtxbusy r/w r r r r r/w r/w r/w r/w rtcrst 0 0 0 0 1 1 1 1 other resets00001111 bit 76543210 name reserved reserved reserved reserved movrrn mrxbend mrxfifof mrxbusy r/w r r r r r/w r/w r/w r/w rtcrst 0 0 0 0 1 1 1 1 other resets00001111 bit name function 15 to 12 reserved 0 is returned after read 11 mundrn mask of transmit fifo underrun interrupt requests 0 : unmasked 1 : masked 10 mtxbend mask of transmit burst end interrupt requests 0 : unmasked 1 : masked 9 mtxfifoe mask of transmit fifo empty interrupt requests 0 : unmasked 1 : masked 8 mtxbusy mask of transmit shift register busy interrupt requests 0 : unmasked 1 : masked 7 to 4 reserved 0 is returned after read 3 movrrn mask of receive fifo overrun interrupt requests 0 : unmasked 1 : masked 2 mrxbend mask of receive burst end interrupt requests 0 : unmasked 1 : masked 1 mrxfifof mask of receive fifo full interrupt requests 0 : unmasked 1 : masked 0 mrxbusy mask of receive shift register busy interrupt requests 0 : unmasked 1 : masked chapter 8 clocked serial interface unit (csi) user ? s manual u14272ej3v0um 167 8.3.6 csiintstat (0x0b00 090a) (1/2) bit 151413121110 9 8 name reserved reserved reserved reserved urnint t xbeint txfeint txbsyint r/w r r r r r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit 76543210 name reserved reserved reserved reserved ornint rxbeint rxffint r xbsyint r/w r r r r r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit name function 15 to 12 reserved 0 is returned after read 11 urnint transmit fifo underrun interrupt request status 0 : not pending 1 : pending this bit is cleared by writing 1. 10 txbeint transmit burst end interrupt request status 0 : not pending 1 : pending this bit is cleared by writing 1. 9 txfeint transmit fifo empty interrupt request status 0 : not pending 1 : pending this bit is cleared by writing 1. 8 txbsyint transmit shift register busy interrupt request status 0 : not pending 1 : pending this bit is cleared by writing 1. 7 to 4 reserved 0 is returned after read 3 ornint receive fifo overrun interrupt request status 0 : not pending 1 : pending this bit is cleared by writing 1. chapter 8 clocked serial interface unit (csi) user ? s manual u14272ej3v0um 168 (2/2) bit name function 2 rxbeint receive burst end interrupt request status 0 : not pending 1 : pending this bit is cleared by writing 1. 1 rxffint receive fifo full interrupt request status 0 : not pending 1 : pending this bit is cleared by writing 1. 0 rxbsyint receive shift register busy interrupt request status 0 : not pending 1 : pending this bit is cleared by writing 1. chapter 8 clocked serial interface unit (csi) user ? s manual u14272ej3v0um 169 8.3.7 csitxblen (0x0b00 090c) bit 151413121110 9 8 name txbln15 txbln14 txbln13 txbln12 txbln11 txbln10 txbln9 txbln8 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit 76543210 name txbln7 txbln6 txbln5 txbln4 txbln3 txbln2 txbln1 txbln0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit name function 15 to 0 txbln(15:0) transmit burst length. these bits determine the number of bits transmitted during one burst cycle. 0x0000 : reserved 0x0001 : 1 bit 0x0002 : 2 bits : : 0x00fd : 253 bits 0x00fe : 254 bits 0x00ff : 255 bits : : 0xfffd : 65533 bits 0xfffe : 65534 bits 0xffff : 65535 bits chapter 8 clocked serial interface unit (csi) user ? s manual u14272ej3v0um 170 8.3.8 csirxblen (0x0b00 090e) bit 151413121110 9 8 name rxbln15 rxbln14 rxbln13 rxbln12 rxbln11 rxbln10 rxbln9 rxbln8 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit 76543210 name rxbln7 rxbln6 rxbln5 rxbln4 rxbln3 rxbln2 rxbln1 rxbln0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit name function 15 to 0 rxbln(15:0) receive burst length. these bits determine the number of bits received during one burst cycle. 0x0000 : reserved 0x0001 : 1 bit 0x0002 : 2 bits : : 0x00fd : 253 bits 0x00fe : 254 bits 0x00ff : 255 bits : : 0xfffd : 65533 bits 0xfffe : 65534 bits 0xffff : 65535 bits user?s manual u14272ej3v0um 171 chapter 9 interrupt control unit (icu) 9.1 overview the icu collects interrupt requests from the various on-chip peripheral units and transfers them with internal interrupt request signals (int0, int1, int2, int3, int4, and nmi) to the cpu core. the signals used to notice interrupt requests to the cpu are as below. nmi: battint only. however, the signal for battint can be switched between nmi and int0 is enabled according to nmireg register?s settings. because nmi?s interrupt masking cannot be controlled by means of software, switch to int0 to mask battint. int4: not used (fixed to 1 (inactive)) int3: not used (fixed to 1 (inactive)) int2: rtclong2 only (rtclong2 timer) int1: rtclong1 only (rtclong1 timer) int0: all other interrupts. for details of the interrupt sources, see 9.2 register set . how an interrupt request is notified to the cpu core is shown below. if an interrupt request occurs in the peripheral units, the corresponding bit in the interrupt indication register of level 2 (xxxintreg) is set to 1. the interrupt indication register is anded bit-wise with the corresponding interrupt mask register of level 2 (mxxxintreg). if the occurred interrupt request is enabled (set to 1) in the mask register, the interrupt request is notified to the interrupt indication register of level 1 (sysintreg) and the corresponding bit is set to 1. at this time, the interrupt requests from the same register of level 2 are notified to the sysintreg as a single interrupt request. interrupt requests from some units directly set their corresponding bits in the sysintreg. the sysintreg is anded bit-wise with the interrupt mask register of level 1 (msysintreg). if the interrupt request is enabled (set to 1) in the msysintreg, a corresponding interrupt request signal is output from the icu to the cpu core. battintr is connected to the nmi or int0 signal of the cpu core (selected by setting of nmireg). rtclong2 and rtclong1 signals are connected to the int2 or int1 signal of the cpu core. the other interrupt requests are connected to the int0 signal of the cpu core as a single interrupt request. the following figure shows an outline of interrupt control in the icu. chapter 9 interrupt control unit (icu) user?s manual u14272ej3v0um 172 figure 9-1. outline of interrupt control ecuint nmireg and and/or and/or siuint etimerint dozepiuint giuint mpiuintreg piuintreg maiuintreg aiuintreg dmaint dual stage synchronizer int2 int1 nmi int0 msysint1reg msysint2reg battint powerint rtclong2int rtclong1int csuint sysint1reg sysint2reg lcdint ledint and/or mkiuintreg kiuintreg dual stage synchronizer softintreg selector and/or and tclock masterclock 3 5 and 10 10 4 4 level 2 registers and signals from peripheral units level 1 registers 8 3 3 3 3 6 6 chapter 9 interrupt control unit (icu) user ? s manual u14272ej3v0um 173 9.2 register set table 9-1. icu registers physical address r/w register symbol function 0x0a00 0080 r sysint1reg level 1 system register 1 0x0a00 008c r/w msynt1reg level 1 mask system register 1 0x0a00 0098 r/w nmireg nmi register 0x0a00 009a r/w softintreg software interrupt register 0x0a00 0200 r sysint2reg level 1 system register 2 0x0a00 0206 r/w msysint2reg level 1 mask system register 2 0x0b00 0082 r piuintreg level 2 piu register 0x0b00 0084 r aiuintreg level 2 aiu register 0x0b00 0086 r/w kiuintreg level 2 kiu register 0x0b00 008e r/w mpiuintreg level 2 mask piu register 0x0b00 0090 w maiuintreg level 2 mask aiu register 0x0b00 0092 r/w mkiuintreg level 2 mask kiu register chapter 9 interrupt control unit (icu) user ? s manual u14272ej3v0um 174 9.2.1 sysint1reg (0x0a00 0080) (1/2) bit 151413121110 9 8 name reserved reserved dozepiu intr reserved softintr reserved siuintr giuintr r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit 76543210 name kiuintr aiuintr piuintr reserved etimer intr rtcl1 intr power intr batintr r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit name function 15, 14 reserved 0 is returned when read 13 dozepiuintr piu interrupt request during suspend mode 0 : not occurred 1 : occurred 12 reserved 0 is returned when read 11 softintr software interrupt request 0 : not occurred 1 : occurred 10 reserved 0 is returned when read 9 siuintr siu interrupt request 0 : not occurred 1 : occurred 8 giuintr giu interrupt request 0 : not occurred 1 : occurred 7 kiuintr kiu interrupt request 0 : not occurred 1 : occurred 6 aiuintr aiu interrupt request 0 : not occurred 1 : occurred chapter 9 interrupt control unit (icu) user ? s manual u14272ej3v0um 175 (2/2) bit name function 5 piuintr piu interrupt request 0 : not occurred 1 : occurred 4 reserved 0 is returned when read 3 etimerintr elapsedtime interrupt request 0 : not occurred 1 : occurred 2 rtcl1intr rtclong1 interrupt request 0 : not occurred 1 : occurred 1 powerintr power switch interrupt request 0 : not occurred 1 : occurred 0 batintr battery low interrupt request 0 : not occurred 1 : occurred this register indicates level-1 interrupt requests ? status. chapter 9 interrupt control unit (icu) user ? s manual u14272ej3v0um 176 9.2.2 msysint1reg (0x0a00 008c) (1/2) bit 151413121110 9 8 name reserved reserved mdozepiu intr reserved msoft intr reserved msiuintr mgiuintr r/w r r r/w r r/w r r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit 76543210 name mkiuintr maiuintr mpiuintr reserved metimer intr mrtcl1 intr mpower intr mbatintr r/w r/w r/w r/w r r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit name function 15, 14 reserved 0 is returned when read 13 mdozepiuintr enables piu interrupt during suspend mode 0 : disable 1 : enable 12 reserved 0 is returned when read 11 msoftintr enables software interrupt 0 : disable 1 : enable 10 reserved 0 is returned when read 9 msiuintr enables siu interrupt 0 : disable 1 : enable 8 mgiuintr enables giu interrupt 0 : disable 1 : enable 7 mkiuintr enables kiu interrupt 0 : disable 1 : enable 6 maiuintr enables aiu interrupt 0 : disable 1 : enable chapter 9 interrupt control unit (icu) user ? s manual u14272ej3v0um 177 (2/2) bit name function 5 mpiuintr enables piu interrupt 0 : disable 1 : enable 4 reserved 0 is returned when read 3 metimerintr enables elapsedtime interrupt 0 : disable 1 : enable 2 mrtcl1intr enables rtclong1 interrupt 0 : disable 1 : enable 1 mpowerintr enables power switch interrupt 0 : disable 1 : enable 0 mbatintr enables battery low interrupt 0 : disable 1 : enable this register is used to enable/disable level-1 interrupts. chapter 9 interrupt control unit (icu) user ? s manual u14272ej3v0um 178 9.2.3 nmireg (0x0a00 0098) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit 76543210 name reserved reserved reserved reserved reserved reserved reserved nmiorint r/w rrrrrrrr/w rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit name function 15 to 1 reserved 0 is returned when read 0 nmiorint battery low interrupt request routing 0 : nmi 1 : int0 this register is used to set the interrupt request signal used to notify the v r 4110 cpu core when a battery low interrupt request has occurred. chapter 9 interrupt control unit (icu) user ? s manual u14272ej3v0um 179 9.2.4 softintreg (0x0a00 009a) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit 76543210 name reserved reserved reserved reserved reserved reserved reserved softintr r/w rrrrrrrw rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit name function 15 to 1 reserved 0 is returned when read 0 softintr set/clear a software interrupt request. this bit is a write-only bit. software interrupt request pending status is reported in the sysint1reg (0x0a000080). 0 : clear 1 : set this register is used to set a software interrupt request. chapter 9 interrupt control unit (icu) user ? s manual u14272ej3v0um 180 9.2.5 sysint2reg (0x0a00 0200) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit 76543210 name reserved lcdintr dmaintr reserved csuintr ecuintr ledintr rtcl2intr r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit name function 15 to 7 reserved 0 is returned when read 6 lcdintr lcd interrupt request 0 : not occurred 1 : occurred 5 dmaintr dma interrupt request 0 : not occurred 1 : occurred 4 reserved 0 is returned when read 3 csuintr csi interrupt request 0 : not occurred 1 : occurred 2 ecuintr compactflash interrupt request 0 : not occurred 1 : occurred 1 ledintr led interrupt request 0 : not occurred 1 : occurred 0 rtcl2intr rtclong2 interrupt request 0 : not occurred 1 : occurred this register indicates level-1 interrupt requests ? status. chapter 9 interrupt control unit (icu) user ? s manual u14272ej3v0um 181 9.2.6 msysint2reg (0x0a00 0206) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit 76543210 name reserved mlcdintr mdmaintr reserved mcsuintr mecuintr mledintr mrtcl2 intr r/w r r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit name function 15 to 7 reserved 0 is returned when read 6 mlcdintr enables lcd interrupt 0 : disable 1 : enable 5 mdmaintr enables dma interrupt 0 : disable 1 : enable 4 reserved write 0 when write. 0 is returned when read 3 mcsuintr enables csi interrupt 0 : disable 1 : enable 2 mecuintr enables compactflash interrupt 0 : disable 1 : enable 1 mledintr enables led interrupt 0 : disable 1 : enable 0 mrtcl2intr enables rtclong2 interrupt 0 : disable 1 : enable this register is used to enable/disable level-1 interrupts. chapter 9 interrupt control unit (icu) user ? s manual u14272ej3v0um 182 9.2.7 piuintreg (0x0b00 0082) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit 76543210 name reserved padcmd intr padadp intr padpage1 intr padpage0 intr paddlost intr reserved penchg intr r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit name function 15 to 7 reserved 0 is returned when read 6 padcmdintr piu command scan interrupt request. this interrupt request occurs when a valid data is detected during a command scan. 0 : not occurred 1 : occurred 5 padadpintr piu ad port scan interrupt request. this interrupt request occurs when a valid data is obtained during an a/d port scan. 0 : not occurred 1 : occurred 4 padpage1intr piu data buffer page 1 interrupt request. this interrupt request occurs when a set of valid data is stored in the page 1 of the data buffer. 0 : not occurred 1 : occurred 3 padpage0intr piu data buffer page 0 interrupt request. this interrupt request occurs when a set of valid data is stored in the page 0 of the data buffer. 0 : not occurred 1 : occurred 2 paddlostintr data loss interrupt request. this interrupt request occurs when a set of data cannot be obtained within the specified time. 0 : not occurred 1 : occurred 1 reserved 0 is returned when read 0 penchgintr touch panel contact status change interrupt request. 0 : not occurred 1 : occurred this register indicates when various piu-related interrupt requests (level 2) occur. chapter 9 interrupt control unit (icu) user ? s manual u14272ej3v0um 183 9.2.8 aiuintreg (0x0b00 0084) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved intmidle intmst r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit 76543210 name reserved reserved reserved reserved reserved reserved intsidle reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit name function 15 to 10 reserved 0 is returned when read 9 intmidle audio input (microphone) idle interrupt request (received data is lost). this interrupt request occurs if a valid data exists in the midatreg register when data is received from the a/d converter. 0 : not occurred 1 : occurred 8 intmst audio input (microphone) receive completion interrupt request. this interrupt request occurs when a 10-bit converted data from the a/d converter is received. 0 : not occurred 1 : occurred 7 to 2 reserved 0 is returned when read 1 intsidle audio output (speaker) idle interrupt request (mute). this interrupt request occurs if there is no valid data in the sodatreg register when data is transferred to the d/a converter. 0 : not occurred 1 : occurred 0 reserved 0 is returned when read this register indicates when various aiu-related interrupt requests occur. chapter 9 interrupt control unit (icu) user ? s manual u14272ej3v0um 184 9.2.9 kiuintreg (0x0b00 0086) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit 76543210 name reserved reserved reserved reserved reserved kdatlost kdatrdy kdownint r/w r r r r r r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit name function 15 to 3 reserved 0 is returned when read 2 kdatlost keyboard data lost interrupt request. this interrupt request occurs if the kiudat0 register is updated with the next key data prior to being read by the cpu core. 0 : not occurred 1 : occurred this bit is cleared by writing 1. 1 kdatrdy keyboard data ready interrupt request. this interrupt request occurs when a set of scanning is completed and all the kiudat registers are updated. 0 : not occurred 1 : occurred this bit is cleared by writing 1. 0 kdownint key down interrupt request. this interrupt request occurs when the kiu sequencer is idle and any of the scanin inputs has been sampled as low level. 0 : not occurred 1 : occurred this bit is cleared by writing 1. the kdatlost bit is also cleared when the kiudat0 register is read. chapter 9 interrupt control unit (icu) user ? s manual u14272ej3v0um 185 9.2.10 mpiuintreg (0x0b00 008e) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit 76543210 name reserved padcmd intr padadp intr padpage1 intr padpage0 intr paddlost intr reserved penchg intr r/w r r/w r/w r/w r/w r/w r r/w rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit name function 15 to 7 reserved 0 is returned when read 6 padcmdintr enables piu command scan interrupt 0 : disable 1 : enable 5 padadpintr enables piu a/d port scan interrupt 0 : disable 1 : enable 4 padpage1intr enables piu data buffer page 1 interrupt 0 : disable 1 : enable 3 padpage0intr enables piu data buffer page 0 interrupt 0 : disable 1 : enable 2 paddlostintr enables data loss interrupt 0 : disable 1 : enable 1 reserved 0 is returned when read 0 penchgintr enables touch panel contact status change interrupt 0 : disable 1 : enable this register is used to mask various piu-related interrupts. chapter 9 interrupt control unit (icu) user ? s manual u14272ej3v0um 186 9.2.11 maiuintreg (0x0b00 0090) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved intmidle intmst r/w wwwwwwww rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit 76543210 name reserved reserved reserved reserved reserved reserved intsidle reserved r/w wwwwwwww rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit name function 15 to 10 reserved write 0 when write 9 intmidle enables audio input (microphone) idle interrupt (received data is lost) 0 : disable 1 : enable 8 intmst enables audio input (microphone) receive completion interrupt 0 : disable 1 : enable 7 to 2 reserved write 0 when write 1 intsidle enables audio output (speaker) idle interrupt (mute) 0 : disable 1 : enable 0 reserved write 0 when write this register is used to mask various aiu-related interrupts. this register is a write-only register and its contents when it is read are undefined. chapter 9 interrupt control unit (icu) user ? s manual u14272ej3v0um 187 9.2.12 mkiuintreg (0x0b00 0092) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit 76543210 name reserved reserved reserved reserved reserved mskkdat lost mskkdat rdy mskk downint r/w r r r r r r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit name function 15 to 3 reserved 0 is returned when read 2 mskkdatlost enables keyboard data lost interrupt 0 : disable 1 : enable this bit may be used to temporarily mask the keyboard data lost interrupt request and does not affect keyboard data lost event detection. 1 mskkdatrdy enables keyboard data ready interrupt 0 : disable 1 : enable this bit may be used to temporarily mask the keyboard data ready interrupt request and does not affect keyboard data ready event detection. 0 mskkdownint enables key down interrupt 0 : disable 1 : enable this bit may be used to temporarily mask the key down interrupt request and does not affect key down event detection. user?s manual u14272ej3v0um 188 chapter 10 power management unit (pmu) this chapter describes the power management unit (pmu) operation, register settings and power modes. 10.1 general the pmu performs power management within the v r 4181 and controls the power supply throughout the system. the pmu provides the following functions: ? reset control ? shutdown control ? power-on control ? low-power mode control 10.2 v r 4181 power mode this section describes the v r 4181 power modes in detail. the v r 4181 supports the following four power modes: ? fullspeed mode ? standby mode ? suspend mode ? hibernate mode 10.2.1 power mode and state transition the v r 4181 transits from fullspeed mode to standby mode, suspend mode, or hibernate mode by executing a stanby, suspend, or hibernate instruction respectively. an rtc reset is always valid in every mode, and initializes (resets) units in the v r 4181 including the rtc. the figure on the following page, figure 10-1, is a conceptual diagram showing the interaction and control of the four power modes of the v r 4181. chapter 10 power management unit (pmu) user?s manual u14272ej3v0um 189 figure 10-1. transition of v r 4181 power mode standby mode suspend mode fullspeed mode hibernate mode (3) (4) (2) (6) (5) (1) rtc reset (8) (9) (7) transition no. factors (1) standby instruction (2) all interrupt requests (3) suspend instruction chapter 10 power management unit (pmu) user ? s manual u14272ej3v0um 190 table 10-1 shows power mode overview and transaction: table 10-1. overview of power modes mode internal peripheral unit cpu core rtc icu dma lcdc others fullspeed on on on on selectable on standby on on on on selectable off suspend on on off off off off hibernate on off off off off off off off off off off off off (1) fullspeed mode all internal clocks and bus clocks operate. the v r 4181 can perform every function during the fullspeed mode. (2) standby mode the pipeline clock (pclock) of the cpu core is fixed to high level. pll, timer/interrupt function of the cpu core, interrupt clock (masterout), internal bus clock (tclock and pclk), and rtc clock continue their operation. therefore, all the on-chip peripheral units continue their operation (operation of the lcd controller and dma also continue). the contents of caches and registers in the cpu core are retained. to enter to standby mode from fullspeed mode, execute the standby instruction. after the standby instruction has passed the wb stage, the v r 4181 waits until sysad bus (internal) enters idle state. then, internal clocks are shut down, and pipeline operation stops. to restore to fullspeed mode, generate an interrupt request of any kind. when the processor restores to fullspeed mode from standby mode, it starts a program execution from the general exception vector (0xbfc0 0380 when bev = 0 or 0x8000 0180 when bev = 1). (3) suspend mode the pipeline clock (pclock) of the cpu core and the internal bus clocks (tclock and pclk) are fixed to high level. pll, timer/interrupt function of the cpu core, interrupt clock (masterout), and rtc clock continue their operation. the contents of caches and registers in the cpu core are retained. the contents of connected drams can be preserved by putting drams into self-refresh mode. to enter to suspend mode from fullspeed mode, execute a suspend mode sequence (see 10.6 dram interface control ) first. after the suspend instruction has passed the wb stage and drams enter self-refresh mode, the v r 4181 waits until sysad bus (internal) enters idle state. then, internal clocks are shut down, and pipeline operation stops. to restore to fullspeed mode from suspend mode, one of the interrupt requests listed in figure 10-1 (interrupt requests that can be used are limited since the internal bus clocks (tclock and pclk) stop). when the processor restores to fullspeed mode from suspend mode, it starts a program execution from the general exception vector (0xbfc0 0380 when bev = 0 or 0x8000 0180 when bev = 1). chapter 10 power management unit (pmu) user ? s manual u14272ej3v0um 191 (4) hibernate mode all clocks other than the rtc clock (32.768 khz) are fixed to high level and the pll operation stops. an rtc and a monitor for activation factors in the pmu continue their operation. to enter to hibernate mode from fullspeed mode, execute a hibernate mode sequence (see 10.6 dram interface control ) first. after the hibernate instruction has passed the wb stage and drams enter self- refresh mode, the v r 4181 waits until sysad bus (internal) enters idle state. then, mpower signal becomes inactive after internal clocks are shut down and pipeline operation stops. 2.5 v power supply can be stopped during mpower signal is inactive. if it is stopped, however, the contents of registers in the peripheral units other than pmu, giu, led, and rtc are not retained. to restore to fullspeed mode from hibernate mode, one of the interrupt requests listed in figure 10-1. when the processor restores to fullspeed mode from hibernate mode, it starts a program execution from the cold reset exception vector (0xbfc0 0000). 10.3 reset control the operations of the rtc, peripheral units, and cpu core, and pmuintreg register bit settings during a reset are listed below. table 10-2. operations during reset reset type rtc, giu peripheral units cpu core pmuintreg bits rtc reset reset reset cold reset rtcrst = 1 rstsw reset 1 active reset cold reset rstsw = 1 sdram = 0 rstsw reset 2 active active cold reset rstsw = 1 sdram = 1 deadman ? s switch reset active reset cold reset dmsrst = 1 caution when bit 6 of the pmuintreg register is set to 1, only the cpu core is reset during a rstsw reset cycle, and all internal peripheral units retain their current state. software must re-initialize or reset all peripheral units in this case. to preserve sdram data during a rstsw reset, bit 6 of the pmuintreg register should be set to 1 when sdram is used. 10.3.1 rtc reset when the rtcrst# signal becomes active, the pmu resets all internal peripheral units including the rtc unit. it also resets (cold reset) the cpu core. in addition, the rtcrst bit in the pmuintreg register is set to 1. after the cpu core is restarted, the rtcrst bit must be checked and cleared to 0 by software. for details of the timing of rtc reset, refer to chapter 5 initialization interface . chapter 10 power management unit (pmu) user ? s manual u14272ej3v0um 192 10.3.2 rstsw reset when the rstsw# signal becomes active, the pmu resets (cold reset) the cpu core. when bit 6 of the pmuintreg register is cleared to 0, the pmu also resets all internal peripheral units except for the rtc and giu. in addition, the rstsw bit in the pmuintreg register is set to 1. after the cpu core is restarted, the rstsw bit must be checked and cleared to 0 by software. for details of the timing of rstsw reset, refer to chapter 5 initialization interface . 10.3.3 deadman?s switch reset when the deadman ? s switch function is enabled, software must write 1 to dswclr bit in the dsuclrreg register each set time, to clear the deadman ? s switch counter (for more information, refer to chapter 12 deadman?s switch unit (dsu) ). if the deadman ? s switch counter is not cleared within the set time, the pmu resets all peripheral units except for rtc, giu, and pmu. then the pmu resets (cold reset) the cpu core. in addition, dmsrst bit in the pmuintreg register is set to 1. after the cpu core is restarted, dmsrst bit must be checked and cleared to 0 by software. 10.3.4 preserving dram data on rstsw reset (1) preserving edo-dram data when an rstsw reset takes place, the pmu activates the cas#/ras# pins to generate a cbr self refresh request to edo dram. remark there is no burst cbr refresh before and after cbr self refresh by rstsw reset. figure 10-2. edo dram signals on rstsw reset (sdram bit = 0) ras(1:0)# (output) cas# (output) rstsw# (input) rtc (internal) (2) preserving sdram data the sdram bit of the pmuintreg register can be used to preserve the contents of sdram connected to the v r 4181 during an rstsw reset. when the sdram bit is set to 1, the pmu does not reset the memory controller. therefore, the memory controller completes current sdram access and performs cbr refresh cycle on an rstsw reset. on the other hand, when the sdram bit is set to 0, the memory controller is reset regardless of accesses under processing and does not perform cbr refresh cycle (sdram data will be destroyed). chapter 10 power management unit (pmu) user ? s manual u14272ej3v0um 193 10.4 shutdown control the operations of the rtc, peripheral units, and cpu core, and pmuintreg register bit settings during a reset are listed below. for detail of the timing of each shutdown, refer to chapter 5 initialization interface . table 10-3. operations during shutdown shutdown type rtc, giu peripheral units cpu core pmuintreg bits haltimer shutdown active reset cold reset timoutrst = 1 software shutdown active reset cold reset ? battinh shutdown active reset cold reset battinh = 1 10.4.1 haltimer shutdown after the cpu core is activated (following the mode change from shutdown or hibernate mode to fullspeed mode), or the cpu core is reset by rstsw reset, software must write 1 to haltimerrst bit in the pmucntreg register within about four seconds to clear the haltimer. if the haltimer is not reset within about four seconds after the cpu core is activated or the rstsw reset is canceled, the pmu resets all peripheral units except for rtc and pmu. then the pmu resets (cold reset) the cpu core. in addition, timoutrst bit in pmuintreg register is set to 1. after the cpu core is restarted, timoutrst bit must be checked and cleared to 0 by software. 10.4.2 software shutdown when the hibernate instruction is executed, the pmu checks for currently pending interrupt requests. if there are no pending interrupt requests, it stops the cpu core clock. it then resets all peripheral units except for the rtc, giu, and the pmu. the pmu register contents do not change. 10.4.3 battinh shutdown if the battinh signal is asserted when the cpu core is going to be activated, the pmu stops cpu activation and resets all peripheral units except for the rtc, giu, and the pmu. then it resets the cpu core. in addition, battinh bit in the pmuintreg register is set to 1. after the cpu core is restarted, battinh bit must be checked and cleared to 0 by software. for details of the timing of battinh shutdown, see 10.5 power-on control below. chapter 10 power management unit (pmu) user ? s manual u14272ej3v0um 194 10.5 power-on control the causes of cpu core activation (mode change from shutdown mode or hibernate mode to fullspeed mode) are called activation factors. there are twenty activation factors: a power switch interrupt (power), sixteen types of gpio activation interrupts (gpio(15:0)), a dcd interrupt (dcd#), a compactflash interrupt, and an elapsedtime interrupt. battery low detection (battinh/battint# pin check) is a factor that prevents cpu core activation. the period (power-on wait time) in which the poweron pin is active at power-on can be specified by using pmuwaitreg register. after rtcrst, by which the cpu core is initialized, the period is set as 343.75 ms. power- on wait time can be specified when activation is caused by sources other than rtcrst. when mpower signal is at low level (hibernate mode or during cpu core activation), to stop supplying voltage to the 2.5 v power-supply systems is recommended to reduce leak current. this means that this power supply can be 0 v while the mpower signal is inactive. the following operation will not be affected by supplying voltage of 2.3 v or more to this power supply within the period from when the mpower signal becomes active to when pll starts oscillation. caution when the cpu core enters the hibernate mode by executing the hibernate instruction, if an activation factor occurs simultaneously, the cpu core may be activated without asserting the poweron signal after the mpower signal is once de-asserted. moreover, if rstsw#, which is not an activation factor of the hibernate mode, is asserted at the same time a transition to the hibernate mode by executing the hibernate instruction occurs, the cpu core may be activated without asserting the poweron signal after the mpower signal is de-asserted once. chapter 10 power management unit (pmu) user ? s manual u14272ej3v0um 195 10.5.1 activation via power switch interrupt request when the power signal is asserted, the pmu asserts the poweron signal to provide an external notification that the cpu core is being activated. after asserting the poweron signal, the pmu checks the battinh signal and then de-asserts the poweron signal. if the battinh signal is at high level, the pmu cancels peripheral unit reset and starts the cold reset sequence to activate the cpu core. if the battinh signal is at low level, the pmu sets 1 to the battinh bit in the pmuintreg register and then performs another shutdown. after the cpu core is restarted, the battinh bit must be checked and cleared to 0 by software. remark activation via power switch interrupt request never sets the powerswintr bit in the pmuintreg register to 1. figure 10-3. activation via power switch interrupt request (battinh = h) battinh/battint# (input) mpower (output) poweron (output) power (input) rtc (internal) h figure 10-4. activation via power switch interrupt request (battinh = l) battinh/battint# (input) mpower (output) l l poweron (output) power (input) rtc (internal) chapter 10 power management unit (pmu) user ? s manual u14272ej3v0um 196 10.5.2 activation via compactflash interrupt request when the cf_busy# signal is asserted, the pmu asserts the poweron signal to provide an external notification that the cpu core is being activated. after asserting the poweron signal, the pmu checks the battinh signal and then de-asserts the poweron signal. if the battinh signal is at high level, the pmu cancels peripheral unit reset and starts the cold reset sequence to activate the cpu core. if the battinh signal is at low level, the pmu sets 1 to the battinh bit in the pmuintreg register and then performs another shutdown. after the cpu core is restarted, the battinh bit must be checked and cleared to 0 by software. figure 10-5. activation via compactflash interrupt request (battinh = h) battinh/battint# (input) mpower (output) poweron (output) cf_busy# (input) rtc (internal) h figure 10-6. activation via compactflash interrupt request (battinh = l) battinh/battint# (input) mpower (output) l l poweron (output) cf_busy# (input) rtc (internal) chapter 10 power management unit (pmu) user ? s manual u14272ej3v0um 197 10.5.3 activation via gpio activation interrupt request when any of the gpio(15:0) signals are asserted, the pmu checks the gpio(15:0) activation interrupt enable bits in the giu. if gpio(15:0) activation interrupts are enabled, the pmu asserts the poweron signal to provide an external notification that the cpu core is being activated (since the gpio(15:0) activation enable interrupt bits are cleared after an rtc reset, the gpio(15:0) signal cannot be used for activation immediately after an rtc reset). after asserting the poweron signal, the pmu checks the battinh signal and de-asserts the poweron signal. if the battinh signal is at high level, the pmu cancels the peripheral unit reset and starts the cold reset sequence to activate the cpu core. if the battinh signal is at low level, the pmu sets 1 to the battinh bit in the pmuintreg register and then performs another shutdown. after the cpu core is restarted, the battinh bit must be checked and cleared to 0 by software. the cpu core sets 1 to the gpwakeup bit in the pmuintreg register regardless of whether activation succeeds or fails. caution the changes in the gpio signals are ignored while poweron signal is active. figure 10-7. activation via gpio activation interrupt request (battinh = h) battinh/battint# (input) mpower (output) poweron (output) gpio (15:0) (i/o) rtc (internal) h figure 10-8. activation via gpio activation interrupt request (battinh = l) battinh/battint# (input) mpower (output) poweron (output) gpio (15:0) (i/o) rtc (internal) l l chapter 10 power management unit (pmu) user ? s manual u14272ej3v0um 198 10.5.4 activation via dcd interrupt request when the dcd1# signal is asserted, the pmu asserts the poweron signal to provide an external notification that the cpu core is being activated. after asserting the poweron signal, the pmu checks the battinh signal and then de-asserts the poweron signal. if the battinh signal is at high level, the pmu cancels the peripheral unit reset and starts the cold reset sequence to activate the cpu core. if the battinh signal is at low level, the pmu sets 1 to the battinh bit in the pmuintreg register and then performs another shutdown. after the cpu core is restarted, the battinh bit must be checked and cleared to 0 by software. the dcdst bit in the pmuintreg register does not indicate whether a dcd interrupt has occurred but instead reflects the current status of the dcd1# pin. cautions1. the pmu cannot recognize changes in the dcd1# signal while the power signal is asserted. if the dcd1# state when the power signal is asserted is different from that when the power signal is deasserted, the change in the dcd1# signal is detected only after the power signal is deasserted. however, if the dcd1# state when the power signal is asserted is the same as that when the power signal is deasserted, any changes in the dcd1# signal that occur while the power signal is asserted are not detected. 2. the changes in the dcd1# signal are ignored while the poweron signal is active. 3. there is no indicator which shows an activation via dcd interrupt, if dcd1# signal has already changed from active to inactive during power-on sequence. in other words, if software can not find activation factor and if the dcdst bit indicates that dcd1# signal is active, the above situation occurred. chapter 10 power management unit (pmu) user ? s manual u14272ej3v0um 199 figure 10-9. activation via dcd interrupt request (battinh = h) battinh/battint# (input) mpower (output) poweron (output) dcd1# (input) rtc (internal) h figure 10-10. activation via dcd interrupt request (battinh = l) battinh/battint# (input) mpower (output) l l poweron (output) dcd1# (input) rtc (internal) chapter 10 power management unit (pmu) user ? s manual u14272ej3v0um 200 10.5.5 activation via elapsedtime (rtc alarm) interrupt request when the alarm (alarm_intr signal) generated from the elapsedtime timer is asserted, the pmu asserts the poweron signal to provide an external notification that the cpu core is being activated. after asserting the poweron signal, the pmu checks the battinh signal and then de-asserts the poweron signal. if the battinh signal is at high level, the pmu cancels the peripheral unit reset and starts the cold reset sequence to activate the cpu core. if the battinh signal is at low level, the pmu sets 1 to the battinh bit in the pmuintreg register and then performs another shutdown. after the cpu core is restarted, the battinh bit must be checked and cleared to 0 by software. caution the elapsedtime interrupt is ignored while the poweron signal is active. after the poweron signal becomes inactive, the pmu is notified. figure 10-11. activation via elapsedtime interrupt request (battinh = h) battinh/battint# (input) mpower (output) poweron (output) alam_intr (internal) rtc (internal) h figure 10-12. activation via elapsedtime interrupt request (battinh = l) battinh/battint# (input) mpower (output) l l poweron (output) alam_intr (internal) rtc (internal) chapter 10 power management unit (pmu) user ? s manual u14272ej3v0um 201 10.6 dram interface control the pmu provides a register to control the dram interface during hibernate mode or suspend mode. the dramhibctl register permits software to directly control the state of the dram interface pins prior to executing a hibernate or suspend instruction. the dramhibctl register also provides status indication of the memory controller. the software flow when entering and exiting hibernate mode or suspend mode is shown below. 10.6.1 entering hibernate mode (edo dram) <1> copy contents of all 2.5 v registers (i.e. dram type and configuration, rom type and configuration, etc.) that must be preserved during hibernate mode into the general-purpose registers, miscreg(0:15), in the giu or into external memory. remark 3.3 v peripheral units: pmu, giu, led, and rtc 2.5 v peripheral units: all peripherals except pmu, giu, led, and rtc <2> stop operations of the dma controller and lcd controller. <3> copy the codes for the hibernate mode (<4> through <11> below) beginning at a 16-byte boundary into the cache by using a fill operation of cache instruction, and jump to the cached codes. <4> stop all peripheral clocks by writing zero to the cmuclkmsk register in the mba host bridge. <5> if dram can accept mixed use of burst and distributive cbr refresh, set a value that determines the refresh count to every 250 ns to the bcurfcntreg register in the mba host bridge. then execute cbr refresh cycles for a specific time period (i.e. 0x3fff tclock period + burst refresh interval required by dram). <6> set 0x3ff to the bcurfcntreg register in the mba host bridge that determines refresh interval to maximum to prevent an interruption of a hibernate mode sequence. <7> set the suspend bit in the dramhibctl register to 1. if the bstrefr bit of the memcfg_reg register in the memory controller to 1, the memory controller performs a burst refresh cycle and then put the dram into self-refresh mode. <8> poll the ok_stop_clk bit in the dramhibctl register to confirm that the memory controller completes a burst refresh cycle and put the dram into self-refresh mode. <9> set the stop_clk bit in the dramhibctl register to 1 to stop supplying tclock to the memory controller. <10> set the dram_en bit in the dramhibctl register to 1 so that the dram interface signals are latched. <11> execute a hibernate instruction. <12> stop applying 2.5 v power supply when the mpower signal becomes low level. caution when entering hibernate mode, set the bev bit of the status register in the cp0 of the cpu core to 1 to make sure that the vector of the exception handler points the rom area. chapter 10 power management unit (pmu) user ? s manual u14272ej3v0um 202 10.6.2 entering hibernate mode (sdram) <1> copy contents of all 2.5 v registers (i.e. dram type and configuration, rom type and configuration, etc.) that must be preserved during hibernate mode into the general-purpose registers, miscreg(0:15), in the giu or into external memory. remark 3.3 v peripheral units: pmu, giu, led, and rtc 2.5 v peripheral units: all peripherals except pmu, giu, led, and rtc <2> stop operations of the dma controller and lcd controller. <3> copy the codes for the hibernate mode (<4> through <12> below) beginning at a 16-byte boundary into the cache by using a fill operation of cache instruction, and jump to the cached codes. <4> stop all peripheral clocks by writing zero to the cmuclkmsk register in the mba host bridge. <5> set the bcurfcntreg register in the mba host bridge to a value that determines refresh interval to maximum to prevent an interruption of a hibernate mode sequence. <6> if burst refreshes are needed, set a value that determines the refresh count to every 250 ns to the bcurfcntreg register in the mba host bridge. then execute cbr auto refresh cycles for a specific time period (i.e. 0x3fff tclock period + burst refresh interval required by dram). <7> clear the bstrefr bit of the memcfg_reg register in the memory controller to 0 to disable a burst refresh. then set suspend bit in the dramhibctl register to 1 to put the dram into self-refresh mode. <8> poll the ok_stop_clk bit in the dramhibctl register to confirm that the memory controller puts the dram into self-refresh mode. <9> set the stop_clk bit in the dramhibctl register to 1 to stop supplying tclock to the memory controller. <10> set the dram_en bit in the dramhibctl register to 1 so that the dram interface signals are latched. <11> clear the suspend bit in the dramhibctl register to 0 after waiting for about 2 s. <12> execute a hibernate instruction. <13> stop applying 2.5 v power supply when the mpower signal becomes low level. caution when entering hibernate mode, set the bev bit of the status register in the cp0 of the cpu core to 1 to make sure that the vector of the exception handler points the rom area. chapter 10 power management unit (pmu) user ? s manual u14272ej3v0um 203 10.6.3 exiting hibernate mode (edo dram) <1> generate a wake-up event such as a transition on the power pin, a dcd interrupt, etc. which causes the pmu to start a power-on sequence. <2> apply 2.5 v power supply when the mpower signal becomes high level. the pmu waits until 3.3 v and 2.5 v power supply are stable, and then deasserts the reset signals to the v r 4110 cpu core and on-chip peripheral units. <3> software execution resumes at the cold reset exception vector (0x0bfc 0000). initialize the cache tags, and the config, status, and watchlo registers in the cp0. reset the haltimer by setting the haltimerrst bit in the pmucntreg register to 1. <4> check and clear the timoutrst bit in the pmuintreg register in the case a haltimer shutdown had occurred. <5> copy the codes for the restore (<6> through <12> below) beginning at a 16-byte boundary into the cache by using a fill operation of cache instruction, and jump to the cached codes. these codes can be executed on rom. <6> poll the ok_stop_clk bit in the dramhibctl register until it is set to 1. <7> reinitialize all the registers and peripherals during hibernate mode and restore those registers saved in the general-purpose registers, miscreg(0:15) which retain values during hibernate mode, in the giu or in external memory. remark software must wait until the ok_stop_clk bit in the dramhibctl register is set to 1 before reinitializing the memory controller registers. otherwise unpredictable behavior of the memory controller could result. <8> clear the dram_en bit in the dramhibctl register to 0 so that the dram interface signals are again driven directly by the memory controller. <9> clear suspend bit in the dramhibctl register to 0 to exit self-refresh mode. <10> set the edomcytreg and memcfg_reg registers in the memory controller according to the dram type to be used. <11> if dram can accept mixed use of burst and distributive cbr refresh, set a value that determines the refresh count to every 250 ns to the bcurfcntreg register in the mba host bridge. then execute cbr refresh cycles for a specific time period (i.e. 0x3fff tclock period + burst refresh interval required by dram). <12> restore to the bcurfcntreg register in the mba host bridge a value that determines refresh interval satisfying the conditions of dram type to be used. chapter 10 power management unit (pmu) user ? s manual u14272ej3v0um 204 10.6.4 exiting hibernate mode (sdram) <1> generate a wake-up event such as a transition on the power pin, a dcd interrupt, etc. which causes the pmu to start a power-on sequence. <2> apply 2.5 v power supply when the mpower signal becomes high level. the pmu waits until 3.3 v and 2.5 v power supply are stable, and then deasserts the reset signals to the v r 4110 cpu core and on-chip peripheral units. <3> software execution resumes at the cold reset exception vector (0x0bfc 0000). initialize the cache tags, and the config, status, and watchlo registers in the cp0. reset the haltimer by setting the haltimerrst bit in the pmucntreg register to 1. <4> check and clear the timoutrst bit in the pmuintreg register in the case a haltimer shutdown had occurred. <5> copy the codes for the restore (<6> through <12> below) beginning at a 16-byte boundary into the cache by using a fill operation of cache instruction, and jump to the cached codes. these codes can be executed on rom. <6> reinitialize all the registers and peripherals during hibernate mode and restore those registers saved in the general-purpose registers, miscreg(0:15) which retain values during hibernate mode, in the giu or in external memory. <7> clear the dram_en bit in the dramhibctl register to 0 so that the dram interface signals are again driven directly by the memory controller. <8> sdram exits the self-refresh mode. <9> set the memcfg_reg, mode_reg, and sdtimingreg registers in the memory controller according to the sdram type to be used. <11> if burst refreshes are needed, set a value that determines the refresh count to every 250 ns to the bcurfcntreg register in the mba host bridge. then execute cbr auto refresh cycles for a specific time period (i.e. 0x3fff tclock period + burst refresh interval required by dram). <12> restore to the bcurfcntreg register in the mba host bridge a value that determines refresh interval satisfying the conditions of dram type to be used. chapter 10 power management unit (pmu) user ? s manual u14272ej3v0um 205 10.6.5 entering suspend mode (edo dram) <1> stop operations of the dma controller and lcd controller. <2> set registers in the icu and cp0 to allow notification of the interrupt requests used as wake-up events to fullspeed mode to the cpu core. <3> copy the codes for the suspend mode (<4> through <11> below) beginning at a 16-byte boundary into the cache by using a fill operation of cache instruction, and jump to the cached codes. <4> stop all peripheral clocks by writing zero to the cmuclkmsk register in the mba host bridge. <5> if dram can accept mixed use of burst and distributive cbr refresh, set a value that determines the refresh count to every 250 ns to the bcurfcntreg register in the mba host bridge. then execute cbr refresh cycles for a specific time period (i.e. 0x3fff tclock period + burst refresh interval required by dram). <6> set 0x3ff to the bcurfcntreg register in the mba host bridge that determines refresh interval to maximum to prevent an interruption of a suspend mode sequence. <7> set the suspend bit in the dramhibctl register to 1. if the bstrefr bit of the memcfg_reg register in the memory controller to 1, the memory controller performs a burst refresh cycle and then put the dram into self-refresh mode. <8> poll the ok_stop_clk bit in the dramhibctl register to confirm that the memory controller completes a burst refresh cycle and put the dram into self-refresh mode. <9> set the stop_clk bit in the dramhibctl register to 1 to stop supplying tclock to the memory controller. <10> set the dram_en bit in the dramhibctl register to 1 so that the dram interface signals are latched. <11> execute a suspend instruction. caution when entering suspend mode, set the bev bit of the status register in the cp0 of the cpu core to 1 to make sure that the vector of the exception handler points the rom area. chapter 10 power management unit (pmu) user ? s manual u14272ej3v0um 206 10.6.6 entering suspend mode (sdram) <1> stop operations of the dma controller and lcd controller. <2> set registers in the icu and cp0 to allow notification of the interrupt requests used as wake-up events to fullspeed mode to the cpu core. <3> copy the codes for the suspend mode (<4> through <12> below) beginning at a 16-byte boundary into the cache by using a fill operation of cache instruction, and jump to the cached codes. <4> stop all peripheral clocks by writing zero to the cmuclkmsk register in the mba host bridge. <5> set the bcurfcntreg register in the mba host bridge to a value that determines refresh interval to maximum to prevent an interruption of a suspend mode sequence. <6> if burst refreshes are needed, set a value that determines the refresh count to every 250 ns to the bcurfcntreg register in the mba host bridge. then execute cbr auto refresh cycles for a specific time period (i.e. 0x3fff tclock period + burst refresh interval required by dram). <7> clear the bstrefr bit of the memcfg_reg register in the memory controller to 0 to disable a burst refresh. then set suspend bit in the dramhibctl register to 1 to put the dram into self-refresh mode. <8> poll the ok_stop_clk bit in the dramhibctl register to confirm that the memory controller puts the dram into self-refresh mode. <9> set the stop_clk bit in the dramhibctl register to 1 to stop supplying tclock to the memory controller. <10> set the dram_en bit in the dramhibctl register to 1 so that the dram interface signals are latched. <11> clear the suspend bit in the dramhibctl register to 0 after waiting for about 2 s. <12> execute a suspend instruction. caution when entering suspend mode, set the bev bit of the status register in the cp0 of the cpu core to 1 to make sure that the vector of the exception handler points the rom area. chapter 10 power management unit (pmu) user ? s manual u14272ej3v0um 207 10.6.7 exiting suspend mode (edo dram) <1> generate a wake-up event from suspend mode such as a transition on the power pin, a dcd interrupt, etc. <2> software execution resumes at the general exception vector (0x0bfc 0380 when bev = 1). <3> copy the codes for the restore (<4> through <8> below) beginning at a 16-byte boundary into the cache by using a fill operation of cache instruction, and jump to the cached codes. these codes can be executed on rom. <4> poll the ok_stop_clk bit in the dramhibctl register until it is set to 1. remark software must wait until the ok_stop_clk bit in the dramhibctl register is set to 1 before reinitializing the memory controller registers. otherwise unpredictable behavior of the memory controller could result. <5> clear the dram_en bit in the dramhibctl register to 0 so that the dram interface signals are again driven directly by the memory controller. <6> clear suspend bit in the dramhibctl register to 0 to exit self-refresh mode. <7> if dram can accept mixed use of burst and distributive cbr refresh, set a value that determines the refresh count to every 250 ns to the bcurfcntreg register in the mba host bridge. then execute cbr refresh cycles for a specific time period (i.e. 0x3fff tclock period + burst refresh interval required by dram). <8> restore to the bcurfcntreg register in the mba host bridge a value that determines refresh interval satisfying the conditions of dram type to be used. 10.6.8 exiting suspend mode (sdram) <1> generate a wake-up event from suspend mode such as a transition on the power pin, a dcd interrupt, etc. <2> software execution resumes at the general exception vector (0x0bfc 0380 when bev = 1). <3> copy the codes for the restore (<4> through <7> below) beginning at a 16-byte boundary into the cache by using a fill operation of cache instruction, and jump to the cached codes. these codes can be executed on rom. <4> clear the dram_en bit in the dramhibctl register to 0 so that the dram interface signals are again driven directly by the memory controller. <5> sdram exits the self-refresh mode. <6> if burst refreshes are needed, set a value that determines the refresh count to every 250 ns to the bcurfcntreg register in the mba host bridge. then execute cbr auto refresh cycles for a specific time period (i.e. 0x3fff tclock period + burst refresh interval required by dram). <7> restore to the bcurfcntreg register in the mba host bridge a value that determines refresh interval satisfying the conditions of dram type to be used. chapter 10 power management unit (pmu) user ? s manual u14272ej3v0um 208 10.7 register set the pmu registers are listed below: table 10-4. pmu registers physical address r/w register symbol function 0x0b00 00a0 r/w pmuintreg pmu interrupt status register 0x0b00 00a2 r/w pmucntreg pmu control register 0x0b00 00a8 r/w pmuwaitreg pmu wait counter register 0x0b00 00ac r/w pmudivreg pmu div mode register 0x0b00 00b2 r/w dramhibctl dram hibernate mode control register chapter 10 power management unit (pmu) user ? s manual u14272ej3v0um 209 10.7.1 pmuintreg (0x0b00 00a0) (1/2) bit 151413121110 9 8 name reserved reserved reserved gp wakeup cf_int dcdst rtcintr battinh r/w r r r r/w r/w r r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit 76543210 name reserved sdram timout rst rtcrst rstsw dmsrst battintr power swintr r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit name function 15 to 13 reserved 0 is returned when read 12 gpwakeup gpio interrupt request detection. cleared to 0 when 1 is written. 1 : detected 0 : not detected this bit must be checked and cleared to 0 after the cpu core is restarted. 11 cf_int compactflash interrupt request detection. cleared to 0 when 1 is written. 1 : detected 0 : not detected this bit must be checked and cleared to 0 after the cpu core is restarted. 10 dcdst dcd1# pin state 1 : high level (inactive) 0 : low level (active) 9 rtcintr elapsedtime (rtc alarm) interrupt request detection. cleared to 0 when 1 is written. 1 : detected 0 : not detected this bit must be checked and cleared to 0 after the cpu core is restarted. 8 battinh battery low detection during activation. cleared to 0 when 1 is written. 1 : detected 0 : not detected this bit must be checked and cleared to 0 after the cpu core is restarted. 7 reserved write 0 when write. 0 is returned when read. 6 sdram this bit determines whether the internal peripheral units are reset by rstsw. this bit must be clear to 0 when edo dram is used. 1 : not reset (sdram data preserved during rstsw) 0 : reset (sdram data lost during rstsw) chapter 10 power management unit (pmu) user ? s manual u14272ej3v0um 210 (2/2) bit name function 5 timoutrst haltimer reset request detection. cleared to 0 when 1 is written. 1 : detected 0 : not detected this bit must be checked and cleared to 0 after the cpu core is restarted. 4 rtcrst rtc reset detection. cleared to 0 when 1 is written. 1 : detected 0 : not detected this bit must be checked and cleared to 0 after the cpu core is restarted. 3 rstsw rstsw interrupt request detection. cleared to 0 when 1 is written. 1 : detected 0 : not detected this bit must be checked and cleared to 0 after the cpu core is restarted. 2 dmsrst deadman ? s switch interrupt request detection. cleared to 0 when 1 is written. 1 : detected 0 : not detected this bit must be checked and cleared to 0 after the cpu core is restarted. 1 battintr battery low detection during normal operation. cleared to 0 when 1 is written. 1 : detected 0 : not detected this bit must be checked and cleared to 0 after the cpu core is restarted. 0 powerswintr power switch interrupt request detection. cleared to 0 when 1 is written. 1 : detected 0 : not detected this bit must be checked and cleared to 0 after the cpu core is restarted. this register indicates the statuses of power-on factors and interrupt requests. it also indicates the status of the dcd1# pin. the battintr bit is set to 1 when the battinh/battint# signal becomes low and a battery-low interrupt request occurs during modes other than the hibernate mode (mpower = h). the powerswintr bit is set to 1 when the power signal becomes high and a power switch interrupt request occurs during modes other than the hibernate mode. however, this bit is not set to 1 when the power signal becomes high during the hibernate mode (mpower = l). chapter 10 power management unit (pmu) user ? s manual u14272ej3v0um 211 10.7.2 pmucntreg (0x0b00 00a2) (1/2) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit 76543210 name standby reserved selfrfresh suspend hibernate haltimer rst reserved reserved r/w r/w r/w r r r r/w r r/w rtcrst 0 0 0 0 0 0 0 0 other resets note 0000000 bit name function 15 to 8 reserved 0 is returned when read 7 standby standby mode setting. this setting is performed only for software, and does not affect hardware in any way. 1 : standby mode 0 : normal mode 6 reserved write 0 when write. 0 is returned when read. 5 selfrfresh self refresh status 1 : completed 0 : not completed 4 suspend suspend mode status (always 0 during fullspeed mode) 1 : suspend mode 0 : other than suspend mode 3 hibernate hibernate mode status (always 0 during fullspeed mode) 1 : hibernate mode 0 : other than hibernate mode note holds the value before reset. chapter 10 power management unit (pmu) user ? s manual u14272ej3v0um 212 (2/2) bit name function 2 haltimerrst haltimer reset 1 : reset 0 : set this bit is cleared to 0 automatically after reset of the haltimer note1, 2 . 1 reserved 0 is returned when read 0 reserved write 0 when write. 0 is returned when read. notes1. when the haltimerrst bit is cleared to 0 just after set to 1, the haltimer may not be reset. wait more than 6 rtc clock cycles from writing 1 to writing 0. 2. verify that the haltimerrst bit is 0 before reset the haltimer. when this bit is 1, the haltimer is not reset even if write 1 to this bit. in this case, write 0 to this bit first, then write 1 after more than 6 rtc clock cycles. this register is used to set cpu core shutdown and overall system operations management. the haltimerrst bit must be reset within about four seconds after activation. resetting of the haltimerrst bit indicates that the v r 4181 itself has been activated normally. if the haltimerrst bit is not reset within about four seconds after activation, program execution is regarded as abnormal (possibly due to a runaway) and an automatic shutdown is performed. chapter 10 power management unit (pmu) user ? s manual u14272ej3v0um 213 10.7.3 pmuwaitreg (0x0b00 00a8) bit 151413121110 9 8 name reserved reserved wcount 13 wcount 12 wcount 11 wcount 10 wcount 9 wcount 8 r/w r r r/w r/w r/w r/w r/w r/w rtcrst 0 0 1 0 1 1 0 0 other resets 0 0 note note note note note note bit 76543210 name wcount 7 wcount 6 wcount 5 wcount 4 wcount 3 wcount 2 wcount 1 wcount 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit name function 15, 14 reserved 0 is returned when read 13 to 0 wcount(13:0) activation wait time timer count value activation wait time = wcount(13:0) x (1/32.768) ms note holds the value before reset this register is used to set the activation wait time when the cpu core is activated. this register is set to 0x2c00 (i.e. 343.75 ms activation wait time) after rtc reset. therefore, the 343.75 ms wait time is always inserted as an activation wait time, when the cpu core is activated immediately after rtc reset. the activation wait time can be changed by setting this register for the cpu core activation from the hibernate mode. when this register is set to 0x0, 0x1, 0x2, 0x3, or 0x4, the operation is not guaranteed. software must set the value of this register to greater than 0x4 to assure reliable operation. chapter 10 power management unit (pmu) user ? s manual u14272ej3v0um 214 10.7.4 pmudivreg (0x0b00 00ac) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit 76543210 name reserved reserved reserved reserved reserved div2 div1 div0 r/w r r r r r r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets00000 note note note bit name function 15 to 3 reserved 0 is returned when read 2 to 0 div(2:0) divide mode 111 : rfu 110 : rfu 101 : rfu 100 : rfu 011 : div3 mode 010 : div2 mode 001 : div1 mode 000 : default mode (div2) note holds the value before reset this register is used to set cpu core ? s div mode. the div mode setting determines the division rate of the tclock in relation to the pipeline clock (pclock) frequency. since the contents of this register are cleared to 0 during an rtc reset, the div mode setting always div2 mode just after rtc reset. though the div mode has been set via this register, the setting does not become effective immediately in the processor ? s operations. in order to change div mode, software has to put the cpu core into the hibernate mode. the div mode will change when the cpu core wakes up from the hibernate mode. chapter 10 power management unit (pmu) user ? s manual u14272ej3v0um 215 10.7.5 dramhibctl (0x0b00 00b2) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit 76543210 name reserved reserved reserved reserved ok_stop _clk stop _clk suspend dram_en r/w r r r r r r/w r/w r/w rtcrst 0 0 0 undefined 0 0 0 0 other resets 0 0 0 undefined note note note note bit name function 15 to 5 reserved 0 is returned when read 4 reserved an undefined value is returned when read 3 ok_stop_clk ready to stop clocks 1 : ready (dram is in self refresh mode) 0 : not ready (memc is busy to do burst refresh) 2 stop_clk clock supply for memc 1 : stop 0 : supply 1 suspend self refresh request. this bit is for software request to memc to perform burst refresh and enter self refresh mode 1 : request 0 : not request 0 dram_en dram interface operation enable 1 : disabled 0 : enabled (normal mode) note holds the value before reset user?s manual u14272ej3v0um 216 chapter 11 realtime clock unit (rtc) this chapter describes the rtc unit?s operations and register settings. 11.1 general the rtc unit has a total of three timers, including the following two types. ? rtclong .......... this is a 24-bit programmable counter that counts down by 32.768 khz clock cycle. cycle interrupts can be occurred for up to every 512 seconds. the rtc unit of the v r 4181 includes two rtclong timers. ? elapsedtime..... this is a 48-bit up counter that counts up by 32.768 khz clock cycle. it counts up to 272 years before returning to zero. it includes 48-bit comparator (ecmplreg, ecmpmreg, and ecmphreg) and 48-bit alarm time register (etimelreg, etimemreg, and etimehreg) to enable interrupts to occur at specified times. 11.2 register set the rtc registers are listed below. table 11-1. rtc registers physical address r/w register symbol function 0x0b00 00c0 r/w etimelreg elapsedtime l register 0x0b00 00c2 r/w etimemreg elapsedtime m register 0x0b00 00c4 r/w etimehreg elapsedtime h register 0x0b00 00c8 r/w ecmplreg elapsedtime compare l register 0x0b00 00ca r/w ecmpmreg elapsedtime compare m register 0x0b00 00cc r/w ecmphreg elapsedtime compare h register 0x0b00 00d0 r/w rtcl1lreg rtclong1 l register 0x0b00 00d2 r/w rtcl1hreg rtclong1 h register 0x0b00 00d4 r rtcl1cntlreg rtclong1 count l register 0x0b00 00d6 r rtcl1cnthreg rtclong1 count h register 0x0b00 00d8 r/w rtcl2lreg rtclong2 l register 0x0b00 00da r/w rtcl2hreg rtclong2 h register 0x0b00 00dc r rtcl2cntlreg rtclong2 count l register 0x0b00 00de r rtcl2cnthreg rtclong2 count h register 0x0b00 01de r/w rtcintreg rtc interrupt register each register is described in detail below. chapter 11 realtime clock unit (rtc) user?s manual u14272ej3v0um 217 11.2.1 elapsedtime registers (1) etimelreg (0x0b00 00c0) bit 151413121110 9 8 name etime15 etime14 etime13 etime12 etime11 etime10 etime9 etime8 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00000000 other resets note note note note note note note note bit 76543210 name etime7 etime6 etime5 etime4 etime3 etime2 etime1 etime0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00000000 other resets note note note note note note note note bit name function 15 to 0 etime(15:0) elapsedtime timer bits 15 to 0 note continues counting. (2) etimemreg (0x0b00 00c2) bit 151413121110 9 8 name etime31 etime30 etime29 etime28 etime27 etime26 etime25 etime24 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00000000 other resets note note note note note note note note bit 76543210 name etime23 etime22 etime21 etime20 etime19 etime18 etime17 etime16 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00000000 other resets note note note note note note note note bit name function 15 to 0 etime(31:16) elapsedtime timer bits 31 to 16 note continues counting. chapter 11 realtime clock unit (rtc) user?s manual u14272ej3v0um 218 (3) etimehreg (0x0b00 00c4) bit 151413121110 9 8 name etime47 etime46 etime45 etime44 etime43 etime42 etime41 etime40 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00000000 other resets note note note note note note note note bit 76543210 name etime39 etime38 etime37 etime36 etime35 etime34 etime33 etime32 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00000000 other resets note note note note note note note note bit name function 15 to 0 etime(47:32) elapsedtime timer bits 47 to 32 note continues counting these registers indicate the elapsedtime timer?s value. they count up by a 32.768 khz clock cycle and when a match occurs with the elapsedtime compare registers, an alarm (elapsedtime interrupt) occurs (and the counting continues). a write operation is valid once values have been written to all registers (etimelreg, etimemreg, and etimehreg). these registers have no buffers for read. therefore, an illegal data may be read if the timer value changes during a read operation. when using the read value as a data, be sure to read these registers twice and check that two read vales are the same. when setting these registers again, wait until at least 100 s (three cycles of 32.768 khz clock) have elapsed after the first setting. chapter 11 realtime clock unit (rtc) user?s manual u14272ej3v0um 219 11.2.2 elapsedtime compare registers (1) ecmplreg (0x0b00 00c8) bit 151413121110 9 8 name ecmp15 ecmp14 ecmp13 ecmp12 ecmp11 ecmp10 ecmp9 ecmp8 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00000000 other resets note note note note note note note note bit 76543210 name ecmp7 ecmp6 ecmp5 ecmp4 ecmp3 ecmp2 ecmp1 ecmp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00000000 other resets note note note note note note note note bit name function 15 to 0 ecmp(15:0) value to be compared with elapsedtime timer bits 15 to 0 note holds the value before reset. (2) ecmpmreg (0x0b00 00ca) bit 151413121110 9 8 name ecmp31 ecmp30 ecmp29 ecmp28 ecmp27 ecmp26 ecmp25 ecmp24 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00000000 other resets note note note note note note note note bit 76543210 name ecmp23 ecmp22 ecmp21 ecmp20 ecmp19 ecmp18 ecmp17 ecmp16 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00000000 other resets note note note note note note note note bit name function 15 to 0 ecmp(31:16) value to be compared with elapsedtime timer bits 31 to 16 note holds the value before reset. chapter 11 realtime clock unit (rtc) user?s manual u14272ej3v0um 220 (3) ecmphreg (0x0b00 00cc) bit 151413121110 9 8 name ecmp47 ecmp46 ecmp45 ecmp44 ecmp43 ecmp42 ecmp41 ecmp40 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst10000000 other resets note note note note note note note note bit 76543210 name ecmp39 ecmp38 ecmp37 ecmp36 ecmp35 ecmp34 ecmp33 ecmp32 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00000000 other resets note note note note note note note note bit name function 15 to 0 ecmp(47:32) value to be compared with elapsedtime timer bits 47 to 32 note holds the value before reset. use these registers to set the values to be compared with values in the elapsedtime registers. a write operation is valid once values have been written to all registers (ecmplreg, ecmpmreg, and ecmphreg). when setting these registers again, wait until at least 100 s (three cycles of 32.768 khz clock) have elapsed after the first setting. chapter 11 realtime clock unit (rtc) user?s manual u14272ej3v0um 221 11.2.3 rtclong1 registers (1) rtcl1lreg (0x0b00 00d0) bit 151413121110 9 8 name rtcl1p15 rtcl1p14 rtcl1p13 rtcl1p12 rtcl1p11 rtcl1p10 rtcl1p9 rtcl1p8 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00000000 other resets note note note note note note note note bit 76543210 name rtcl1p7 rtcl1p6 rtcl1p5 rtcl1p4 rtcl1p3 rtcl1p2 rtcl1p1 rtcl1p0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00000000 other resets note note note note note note note note bit name function 15 to 0 rtcl1p(15:0) bits 15 to 0 for rtclong1 timer count cycle note holds the value before reset. chapter 11 realtime clock unit (rtc) user?s manual u14272ej3v0um 222 (2) rtcl1hreg (0x0b00 00d2) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst00000000 other resets note note note note note note note note bit 76543210 name rtcl1p23 rtcl1p22 rtcl1p21 rtcl1p20 rtcl1p19 rtcl1p18 rtcl1p17 rtcl1p16 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00000000 other resets note note note note note note note note bit name function 15 to 8 reserved 0 is returned when read 7 to 0 rtcl1p(23:16) bits 23 to 16 for rtclong1 timer count cycle note holds the value before reset. use these registers to set the rtclong1 timer count cycle. the rtclong1 timer begins its countdown at the value written to these registers. a write operation is valid once values have been written to both registers (rtcl1lreg and rtcl1hreg). when setting these registers again, wait until at least 100 s (three cycles of 32.768 khz clock) have elapsed after the first setting. cautions 1. the rtclong1 timer is stopped when all zeros are written. 2. any combined setting of ?rtcl1hreg = 0x0000? and ?rtcl1lreg = 0x0001, 0x0002, 0x0003, or 0x0004? is prohibited. chapter 11 realtime clock unit (rtc) user?s manual u14272ej3v0um 223 11.2.4 rtclong1 count registers (1) rtcl1cntlreg (0x0b00 00d4) bit 151413121110 9 8 name rtcl1c15 rtcl1c14 rtcl1c13 rtcl1c12 rtcl1c11 rtcl1c10 rtcl1c9 rtcl1c8 r/w rrrrrrrr rtcrst00000000 other resets note note note note note note note note bit 76543210 name rtcl1c7 rtcl1c6 rtcl1c5 rtcl1c4 rtcl1c3 rtcl1c2 rtcl1c1 rtcl1c0 r/w rrrrrrrr rtcrst00000000 other resets note note note note note note note note bit name function 15 to 0 rtcl1c(15:0) rtclong1 timer bits 15 to 0 note continues counting. chapter 11 realtime clock unit (rtc) user?s manual u14272ej3v0um 224 (2) rtcl1cnthreg (0x0b00 00d6) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst00000000 other resets note note note note note note note note bit 76543210 name rtcl1c23 rtcl1c22 rtcl1c21 rtcl1c20 rtcl1c19 rtcl1c18 rtcl1c17 rtcl1c16 r/w rrrrrrrr rtcrst00000000 other resets note note note note note note note note bit name function 15 to 8 reserved 0 is returned when read 7 to 0 rtcl1c(23:16) rtclong1 timer bits 23 to 16 note continues counting. these registers indicate the rtclong1 timer?s values. it counts down by a 32.768 khz clock cycle and begins counting at the value set to the rtclong1 registers. an rtclong1 interrupt occurs when the timer value reaches 0x00 0001 (at which point the timer returns to the start value and continues counting). these registers have no buffers for read. therefore, an illegal data may be read if the timer value changes during a read operation. when using the read value as a data, be sure to read the registers twice and check that two read vales are the same. chapter 11 realtime clock unit (rtc) user?s manual u14272ej3v0um 225 11.2.5 rtclong2 registers (1) rtcl2lreg (0x0b00 00d8) bit 151413121110 9 8 name rtcl2p15 rtcl2p14 rtcl2p13 rtcl2p12 rtcl2p11 rtcl2p10 rtcl2p9 rtcl2p8 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00000000 other resets note note note note note note note note bit 76543210 name rtcl2p7 rtcl2p6 rtcl2p5 rtcl2p4 rtcl2p3 rtcl2p2 rtcl2p1 rtcl2p0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00000000 other resets note note note note note note note note bit name function 15 to 0 rtcl2p(15:0) bits 15 to 0 for rtclong2 timer count cycle note holds the value before reset. chapter 11 realtime clock unit (rtc) user?s manual u14272ej3v0um 226 (2) rtcl2hreg (0x0b00 00da) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst00000000 other resets note note note note note note note note bit 76543210 name rtcl2p23 rtcl2p22 rtcl2p21 rtcl2p20 rtcl2p19 rtcl2p18 rtcl2p17 rtcl2p16 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00000000 other resets note note note note note note note note bit name function 15 to 8 reserved 0 is returned when read 7 to 0 rtcl2p(23:16) bits 23 to 16 for rtclong2 timer count cycle note holds the value before reset. use these registers to set the rtclong2 timer count cycle. the rtclong2 timer begins its countdown at the value written to these registers. a write operation is valid once values have been written to both registers (rtcl2lreg and rtcl2hreg). when setting these registers again, wait until at least 100 s (three cycles of 32.768 khz clock) have elapsed after the first setting. cautions 1. the rtclong2 timer is stopped when all zeros are written. 2. any combined setting of ?rtcl2hreg = 0x0000? and ?rtcl2lreg = 0x0001, 0x0002, 0x0003, or 0x0004? is prohibited. chapter 11 realtime clock unit (rtc) user?s manual u14272ej3v0um 227 11.2.6 rtclong2 count registers (1) rtcl2cntlreg (0x0b00 00dc) bit 151413121110 9 8 name rtcl2c15 rtcl2c14 rtcl2c13 rtcl2c12 rtcl2c11 rtcl2c10 rtcl2c9 rtcl2c8 r/w rrrrrrrr rtcrst00000000 other resets note note note note note note note note bit 76543210 name rtcl2c7 rtcl2c6 rtcl2c5 rtcl2c4 rtcl2c3 rtcl2c2 rtcl2c1 rtcl2c0 r/w rrrrrrrr rtcrst00000000 other resets note note note note note note note note bit name function 15 to 0 rtcl2c(15:0) rtclong2 timer bits 15 to 0 note continues counting. chapter 11 realtime clock unit (rtc) user?s manual u14272ej3v0um 228 (2) rtcl2cnthreg (0x0b00 00de) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst00000000 other resets note note note note note note note note bit 76543210 name rtcl2c23 rtcl2c22 rtcl2c21 rtcl2c20 rtcl2c19 rtcl2c18 rtcl2c17 rtcl2c16 r/w rrrrrrrr rtcrst00000000 other resets note note note note note note note note bit name function 15 to 8 reserved 0 is returned when read 7 to 0 rtcl2c(23:16) rtclong2 timer bits 23 to 16 note continues counting. these registers indicate the rtclong2 timer?s values. it counts down by a 32.768 khz clock cycle and begins counting at the value set to the rtclong2 registers. an rtclong2 interrupt occurs when the timer value reaches 0x00 0001 (at which point the timer returns to the start value and continues counting). these registers have no buffers for read. therefore, an illegal data may be read if the timer value changes during a read operation. when using the read value as a data, be sure to read the registers twice and check that two read vales are the same. chapter 11 realtime clock unit (rtc) user?s manual u14272ej3v0um 229 11.2.7 rtc interrupt register (1) rtcintreg (0x0b00 01de) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst00000000 other resets00000000 bit 76543210 name reserved reserved reserved reserved reserved rtcintr2 rtcintr1 rtcintr0 r/w r r r r r r/w r/w r/w rtcrst00000000 other resets00000 note note note bit name function 15 to 3 reserved 0 is returned when read 2 rtcintr2 rtclong2 interrupt request. cleared to 0 when 1 is written. 1 : occurred 0 : normal 1 rtcintr1 rtclong1 interrupt request. cleared to 0 when 1 is written. 1 : occurred 0 : normal 0 rtcintr0 elapsedtime interrupt request. cleared to 0 when 1 is written. 1 : occurred 0 : normal note holds the value before reset. this register indicates the occurrences of interrupt requests of rtc. user?s manual u14272ej3v0um 230 chapter 12 deadman?s switch unit (dsu) this chapter describes operations and register settings of the dsu (deadman?s switch unit). 12.1 general the dsu detects runaway (endless loop) state of the v r 4181 and resets the v r 4181. use of the dsu allows terminating runaway states that may occur due to software in earlier phase to minimize data loss. 12.2 register set the dsu registers are listed below. table 12-1. dsu registers physical address r/w register symbol function 0x0b00 00e0 r/w dsucntreg dsu control register 0x0b00 00e2 r/w dsusetreg dsu cycle setting register 0x0b00 00e4 w dsuclrreg dsu clear register 0x0b00 00e6 r/w dsutimreg dsu elapsed time register each register is described in detail below. chapter 12 deadman?s switch unit (dsu) user?s manual u14272ej3v0um 231 12.2.1 dsucntreg (0x0b00 00e0) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst00000000 other resets00000000 bit 76543210 name reserved reserved reserved reserved reserved reserved reserved dswen r/w rrrrrrrr/w rtcrst00000000 other resets00000000 bit name function 15 to 1 reserved 0 is returned when read 0 dswen deadman?s switch function enable 1 : enabled 0 : disabled this register is used to enable use of the deadman?s switch function. chapter 12 deadman?s switch unit (dsu) user?s manual u14272ej3v0um 232 12.2.2 dsusetreg (0x0b00 00e2) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst00000000 other resets00000000 bit 76543210 name reserved reserved reserved reserved dedtime3 dedtime2 dedtime1 dedtime0 r/w r r r r r/w r/w r/w r/w rtcrst00000001 other resets00000001 bit name function 15 to 4 reserved 0 is returned when read 3 to 0 dedtime(3:0) deadman?s switch cycle setting 1111 : 15 seconds 1110 : 14 seconds : 0010 : 2 seconds 0001 : 1 second 0000 : setting prohibited this register is used to set the cycle for deadman?s switch function. the deadman?s switch cycle can be set in 1-second units in a range from 1 to 15 seconds. the dswclr bit in the dsuclrreg register must be set by means of software within the cycle time specified in this register. the v r 4181?s operation is undefined when 0x0 has been set to dedtime(3:0). chapter 12 deadman?s switch unit (dsu) user?s manual u14272ej3v0um 233 12.2.3 dsuclrreg (0x0b00 00e4) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst00000000 other resets00000000 bit 76543210 name reserved reserved reserved reserved reserved reserved reserved dswclr r/w rrrrrrrw rtcrst00000000 other resets00000000 bit name function 15 to 1 reserved 0 is returned when read 0 dswclr deadman?s switch timer clear 1 : clear (stops timer) 0 : timer counting the deadman?s switch timer is cleared by setting the dswclr bit in this register to 1. the v r 4181 automatically enters in a cold reset status if 1 is not written to this register within the period specified in the dsusetreg register. in order to restart operation of the timer, the dswclr bit in this register must be cleared to 0. chapter 12 deadman?s switch unit (dsu) user?s manual u14272ej3v0um 234 12.2.4 dsutimreg (0x0b00 00e6) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst00000000 other resets00000000 bit 76543210 name reserved reserved reserved reserved crttime3 crttime2 crttime1 crttime0 r/w r r r r r/w r/w r/w r/w rtcrst00000000 other resets00000000 bit name function 15 to 4 reserved 0 is returned when read 3 to 0 crttime(3:0) current deadman?s switch timer value (elapsed time) 1111 : 15 seconds 1110 : 14 seconds : 0010 : 2 seconds 0001 : 1 second 0000 : setting prohibited this register indicates the elapsed time of the current deadman?s switch timer. chapter 12 deadman?s switch unit (dsu) user?s manual u14272ej3v0um 235 12.3 register setting flow the dsu register setting flow is described below. <1> set the dsu timer count cycle (from 1 to 15 seconds). register: dsusetreg, address: 0x0b00 00e2, data: 0x000x the cpu core will be reset if the timer is not cleared (1 is not written to dsuclrreg register) within this time period. <2> enable the dsu. register: dsucntreg, address: 0x0b00 00e0, data: 0x0001 <3> clear the timer within the time period specified in step 1 above. cancel the clearance of the timer to start another counting. register: dsuclrreg, address: 0x0b00 00e4, data: 0x0001 (timer clear) register: dsuclrreg, address: 0x0b00 00e4, data: 0x0000 (timer operation start) for normal use, repeat step 3. to obtain the current elapsed time, read the contents (4 bits) of the dsutimreg register (address: 0x0b00 00e6). <4> disable the dsu during suspend mode or a shutdown. register: dsucntreg, address: 0x0b00 00e0, data: 0x0000 user?s manual u14272ej3v0um 236 chapter 13 general purpose i/o unit (giu) 13.1 overview 13.1.1 gpio pins and alternate functions the v r 4181 provides 32 general-purpose i/o divided into two groups of 16 pins each. the first group, gpio(15:0) pins, are capable of supporting the following types of functions: ? clocked serial interface (csi) ? serial interface channel 2 ? color lcd interface (upper 4-bit data) or compactflash card detect inputs ? general-purpose outputs ? interrupt/wake-up inputs ? programmable chip selects ? external isa system clock output any of gpio(15:0) pins can be used as interrupt/wake-up inputs. the assignment of interface signals to particular gpio pins is shown in the following table: table 13-1. alternate functions of gpio(15:0) pins gpio pin alternate signal 1 alternate signal 2 definition gpio15 fpd7 cd2# color lcd data bit output or card detect 2 input gpio14 fpd6 cd1# color lcd data bit output or card detect 1 input gpio13 fpd5 ? color lcd data bit output gpio12 fpd4 ? color lcd data bit output gpio11 pcs1# ? programmable chip select 1 output. gpio10 frm sysclk csi frm input or sysclk output gpio9 cts2# ? siu2 cts input gpio8 dsr2# ? siu2 dsr input gpio7 dtr2# ? siu2 dtr output gpio6 rts2# ? siu2 rts output gpio5 dcd2# ? siu2 dcd input gpio4 ?? ? gpio3 pcs0# ? programmable chip select 0 output. gpio2 sck ? csi serial clock input gpio1 so ? csi serial data output gpio0 si ? csi serial data input chapter 13 general purpose i/o unit (giu) user?s manual u14272ej3v0um 237 the second group, gpio(31:16) pins, are capable of supporting the following types of functions: ? external isa i/o interface ? external 16-bit bus sizing signal ? rom chip select ? serial interface channel 1 ? general-purpose input ? general-purpose output remark gpio(31:16) pins can not be used as interrupt/wake-up inputs. the assignment of interface signals to particular gpio pins is shown in the following table: table 13-2. alternate functions of gpio(31:16) pins gpio pin alternate signal 1 alternate signal 2 definition gpio31 dsr1# ? siu1 dsr input gpio30 dtr1# ? siu1 dtr output gpio29 dcd1# ? siu1 dcd input gpio28 cts1# ? siu1 cts input gpio27 rts1# ? siu1 rts output gpio26 txd1 ? siu1 transmit data output gpio25 rxd1 ? siu1 receive data input gpio24 romcs2# ? rom chip select for bank 2 gpio23 romcs1# ? rom chip select for bank 1 gpio22 romcs0# ? rom chip select for bank 0 gpio21 reset# ? external isa reset gpio20 note ube# m external isa upper byte enable or lcd modulation output gpio19 iocs16# ? external isa i/o 16-bit bus sizing gpio18 iordy ? external isa i/o channel ready gpio17 iowr# ? external isa i/o write strobe gpio16 iord# ? external isa i/o read strobe note this signal supports input only. the gpio29/dcd1# pin can be used as an activation (wake-up) factor from hibernate mode if enabled by software. the other pins listed above are only capable of providing general-purpose input or output, or the alternate function listed. chapter 13 general purpose i/o unit (giu) user?s manual u14272ej3v0um 238 13.1.2 i/o direction control for each gpio pin, the giu provides register fields of one buffer enable, gpenn, one output data, gpon, and one input data, gpin. the function of each gpio pin is decoded by 2 register bits in one of the gpio mode registers. the most significant bit, gpnmd1, controls the input/output direction of the gpio pin while the system is powered (during fullspeed, standby, or suspend mode). when this bit is set to 1, the gpio pin is normally configured as an output. during hibernate mode, the gpio buffer enables are controlled by the gphibsth and gphibstl registers. remark n = 0 to 31 13.1.3 general-purpose registers the giu includes sixteen 16-bit general-purpose registers. since the contents of these registers are preserved even during hibernate mode, these registers can be used by system software to save the state of selected registers located in the 2.5 v block prior to entering hibernate mode. once the v r 4181 has resumed from hibernate mode, system software can then restore the state of those 2.5 v registers from the general-purpose registers. the general-purpose registers are located in the address range of 0x0b00 0330 to 0x0b00 034f. 13.2 alternate functions overview 13.2.1 clocked serial interface (csi) the clocked serial interface is enabled by writing to the gpio mode registers and utilizes the following gpio pins: table 13-3. csi interface signals gpio pin csi signal type gpio2 sck input gpio1 so output gpio0 si input gpio10 frm input the gpio10/frm pin provides a multifunction control input option. in one mode, frm determines data direction (transmit or receive). in the other mode, frm prohibits transfer depending on its input level. this mode is set in bit 15, frmen, of the csimode register (address: 0x0b00 0900) (see chapter 8 clocked serial interface unit (csi) ). chapter 13 general purpose i/o unit (giu) user?s manual u14272ej3v0um 239 13.2.2 serial interface channels 1 and 2 the giu also provides pin mapping for the serial interface (equivalent to 16550 uart) channels 1 and 2. the serial interface channel 1 (siu1) is enabled by writing to the gpio mode registers. it utilizes the following gpio pins: table 13-4. serial interface channel 1 (siu1) signals gpio pin siu1 signal type gpio26 txd1 output gpio25 rxd1 input gpio31 dsr1# input gpio30 dtr1# output gpio28 cts1# input gpio27 rts1# output gpio29 dcd1# input the giu drives inputs to the serial interface channel 1 based on the settings in the gpio mode registers and bit 15, loopbk1, of the gpsictl register (address: 0x0b00 031a) (for additional information, see 13.3.14 gpsictl (0x0b00 031a) ). when gpio pins have been assigned to provide the serial interface channel 1 inputs, rxd1, dtr1#, rts1#, and dcd1#, the giu simply passes the signals driven on the gpio pins to the corresponding serial interface channel 1 inputs. otherwise, the giu drives these signals based on the value programmed in the gpsictl register as follows: table 13-5. serial interface channel 1 (siu1) loopback control loopbk1 bit value source for driving siu1 input 0 dsr1#: regdsr1 (bit 9) value cts1#: regcts1 (bit 10) value dcd1#: regdcd1 (bit 8) value rxd1: regrxd1 (bit 11) value 1 dsr1#: dtr1# output cts1#: rts1# output dcd1#: regdcd1 (bit 8) value rxd1: regrxd1 (bit 11) value chapter 13 general purpose i/o unit (giu) user?s manual u14272ej3v0um 240 the serial interface channel 2 (siu2) utilizes the dedicated irdin/rxd2 and irdout/txd2 pins. the line control signals, dtr2#, rts2#, dcd2#, dsr2#, and cts2#, are enabled by writing to the gpio mode registers and are utilized through the following gpio pins: table 13-6. serial interface channel 2 (siu2) signals gpio pin siu2 signal type gpio9 cts2# input gpio8 dsr2# input gpio6 rts2# output gpio5 dcd2# input gpio7 dtr2# output the transmit and receive data signals, txd2 and rxd2, are enabled by writing to the siuirsel_2 register in the siu2. control of the serial interface channel 2 line status inputs is identical to that of the serial interface channel 1. the giu drives inputs to the serial interface channel 2 based on the settings in the gpio mode registers and bit 7, loopbk2, of the gpsictl register (address: 0x0b00 031a) (for additional information, see 13.3.14 gpsictl (0x0b00 031a) ). when gpio pins have been assigned to provide the serial interface channel 2 inputs, dtr2#, rts2#, and dcd2#, the giu simply passes the signals driven on the gpio pins to the corresponding serial interface channel 2 inputs. otherwise, the giu drives these signals based on the value programmed in the gpsictl register as follows: table 13-7. serial interface channel 2 (siu2) loopback control loopbk2 bit value source for driving siu2 input 0 dsr2#: regdsr2 (bit 1) value cts2#: regcts2 (bit 2) value dcd2#: regdcd2 (bit 0) value 1 dsr2#: dtr2# output cts2#: rts2# output dcd2#: regdcd2 (bit 0) value note that the giu does not drive the rxd2 input. this signal is always available to the serial interface as either irdin or rxd2. chapter 13 general purpose i/o unit (giu) user?s manual u14272ej3v0um 241 13.2.3 lcd interface the giu supports two functions for the lcd interface. the first is pin mapping for 8-bit stn color lcd panel support. the second is pin mapping for support of an external lcd controller with integrated frame buffer ram. for additional details about the lcd registers, see chapter 21 lcd controller . (1) stn color lcd interface pin mapping the color lcd panel interface is enabled by writing to the gpio mode registers and utilizes the following gpio pins: table 13-8. stn color lcd interface signals gpio pin lcd signal type gpio(15:12) fpd(7:4) output (2) external lcd controller pin mapping an interface to an external lcd controller can be configured by setting the lcdgpen bit of the lcdgpmode register to 1. in this mode the following internal lcd controller pins are redefined to support the external lcd controller interface: table 13-9. external lcd controller interface signals lcd pin external lcd controller interface signal type shclk lcdcs# output loclk memcs16# input vplcd general-purpose output (vpgpio1) output vpbias general-purpose output (vpgpio0) output the lcdcs# output is generated by the address decode logic in the giu. the address range can be specified by programming the lcdgpmode register. the following address ranges are supported: (1) 0x1338 0000 to 0x133f ffff (512kb) (2) 0x133c 0000 to 0x133f ffff (256kb) (3) 0x133e 0000 to 0x133f ffff (128kb) (4) 0x130a 0000 to 0x130a ffff (64kb, the address space of the pc/at tm is assumed) remark all memory cycles that access the external lcd controller address space are treated as 16-bit cycles. the memcs16# input is provided to support external memory devices (besides the external lcd controller) which need accesses in 16-bit cycles. during an external memory cycle, if the memcs16# input is enabled and asserted, the isa bridge will generate a 16-bit cycle. chapter 13 general purpose i/o unit (giu) user?s manual u14272ej3v0um 242 13.2.4 programmable chip selects the giu provides two programmable chip select signals, pcs(1:0)#. these chip select signals are available on the following gpio pins: table 13-10. programmable chip select signals gpio pin programmable chip select type gpio11 pcs1# output gpio3 pcs0# output each programmable chip select signal can be defined individually as memory- or i/o-mapped, 8- or 16-bit data width, and 1 to 64k bytes of address ranges. the chip selects can also be qualified with i/o or memory read strobes. 13.2.5 16-bit bus cycles the giu generates two internal outputs (gpiocs16_l and gpmemcs16_l) to the internal isa bus to signal the data width of the target of an external isa cycle. the internal isa bus uses these outputs as the iocs16# and memcs16# signals that are and?ed with the outputs from other internal isa units. the gpiocs16_l output is controlled by either a programmable chip select set in the pcsmode register (0x0b00 032c) or iocs16#/gpio19 pin. when one of the programmable chip selects has been defined as i/o mapped and 16-bit data width, the gpiocs16_l output is asserted while the i/o cycle address is within the range specified for the programmable chip select. when the iocs16#/gpio19 pin has been configured as iocs16#, the gpiocs16_l output follows the state of the iocs16# signal. the gpmemcs16_l output is controlled by a programmable chip select or the loclk/memcs16# pin. when one of the programmable chip selects has been defined as memory mapped and 16-bit data width, the gpmemcs16_l output is asserted while the memory cycle address is within the range specified for the programmable chip select. when the loclk/memcs16# pin has been configured as memcs16#, the gpmemcs16_l output follows the state of the memcs16# signal. 13.2.6 general purpose input/output each one of the 32 gpio pins can be defined as a general-purpose input or a general-purpose output. when a pin is configured as a general-purpose output, a corresponding value written to the gpdatlreg register or the gpdathreg register appears on the gpio pin. when a pin is configured as a general-purpose input, a value driven on the gpio pin can be read from its corresponding data bit of the gpdatlreg or gpdathreg register. chapter 13 general purpose i/o unit (giu) user?s manual u14272ej3v0um 243 13.2.7 interrupt requests and wake-up events each of the lower sixteen gpio pins, gpio(15:0), can be defined as an interrupt request input. the giu provides a single asynchronous interrupt request output to the mba host bridge, gpiointr. the mba host bridge is responsible for synchronizing this interrupt request with the masterout clock (internal). the giu provides a total of five registers to support gpio interrupt requests. the interrupt enable register, gpinten, is used to enable interrupt requests on a particular gpio pin. the interrupt mask register, gpintmsk, permits temporary masking of an interrupt request for a particular gpio pin. the interrupt type registers, gpinttyph and gpinttypl, define the interrupt trigger type (edge or level) and the level type (polarity) of the interrupt requests input to the gpio pin. the interrupt status register, gpintstat, allows software to determine the source of the gpio interrupt request. the functions of the enable, mask, polarity, and type bits are shown in the following figure: figure 13-1. gpio(15:0) interrupt request detecting logic enable bit gpio input polarity bit type bit mask bit other gpio interrupt requests gpiointr mux v dd level-triggered interrupt request note note edge-triggered interrupt request during hibernate mode, any one of the gpio(15:0) inputs can be used as a wake-up event. wake-up event notification is asynchronous and output on the gpwakeup signal (internal) note . to enable gpio wake-up events, the following conditions must be met. (1) interrupt requests to the gpio pin must be enabled (set in the gpinten register). (2) interrupt requests to the gpio pin must be unmasked (set in the gpintmsk register). (3) the gpio pin must be enabled during hibernate mode (set in the gphibstl register). note the state of this signal is displayed on the gpwakeup bit of the pmuintreg register in the pmu. chapter 13 general purpose i/o unit (giu) user ? s manual u14272ej3v0um 244 13.3 register set the giu provides the following registers. table 13-11. giu registers (1/2) physical address r/w register symbol function 0x0b00 0300 r/w gpmd0reg gpio mode 0 register 0x0b00 0302 r/w gpmd1reg gpio mode 1 register 0x0b00 0304 r/w gpmd2reg gpio mode 2 register 0x0b00 0306 r/w gpmd3reg gpio mode 3 register 0x0b00 0308 r/w gpdathreg gpio data high register 0x0b00 030a r/w gpdatlreg gpio data low register 0x0b00 030c r/w gpinten gpio interrupt enable register 0x0b00 030e r/w gpintmsk gpio interrupt mask register 0x0b00 0310 r/w gpinttyph gpio interrupt type high register 0x0b00 0312 r/w gpinttypl gpio interrupt type low register 0x0b00 0314 r/w gpintstat gpio interrupt status register 0x0b00 0316 r/w gphibsth gpio hibernate pin status high register 0x0b00 0318 r/w gphibstl gpio hibernate pin status low register 0x0b00 031a r/w gpsictl gpio serial interface control register 0x0b00 031c r/w keyen keyboard scan pin enable register 0x0b00 0320 r/w pcs0stra programmable chip select 0 start address register 0x0b00 0322 r/w pcs0stpa programmable chip select 0 stop address register 0x0b00 0324 r/w pcs0hia programmable chip select 0 high address register 0x0b00 0326 r/w pcs1stra programmable chip select 1 start address register 0x0b00 0328 r/w pcs1stpa programmable chip select 1 stop address register 0x0b00 032a r/w pcs1hia programmable chip select 1 high address register 0x0b00 032c r/w pcsmode programmable chip select mode register 0x0b00 032e r/w lcdgpmode lcd general-purpose mode register chapter 13 general purpose i/o unit (giu) user ? s manual u14272ej3v0um 245 table 13-11. giu registers (2/2) physical address r/w register symbol function 0x0b00 0330 r/w miscreg0 0x0b00 0332 r/w miscreg1 0x0b00 0334 r/w miscreg2 0x0b00 0336 r/w miscreg3 0x0b00 0338 r/w miscreg4 0x0b00 033a r/w miscreg5 0x0b00 033c r/w miscreg6 0x0b00 033e r/w miscreg7 0x0b00 0340 r/w miscreg8 0x0b00 0342 r/w miscreg9 0x0b00 0344 r/w miscreg10 0x0b00 0346 r/w miscreg11 0x0b00 0348 r/w miscreg12 0x0b00 034a r/w miscreg13 0x0b00 034c r/w miscreg14 0x0b00 034e r/w miscreg15 general-purpose register chapter 13 general purpose i/o unit (giu) user ? s manual u14272ej3v0um 246 13.3.1 gpmd0reg (0x0b00 0300) (1/2) bit 151413121110 9 8 name gp7md1 gp7md0 gp6md1 gp6md0 gp5md1 gp5md0 gp4md1 gp4md0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit 76543210 name gp3md1 gp3md0 gp2md1 gp2md0 gp1md1 gp1md0 gp0md1 gp0md0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit name function 15, 14 gp7md(1:0) these bits control direction and function of the gpio7 pin as follows: 00 : general-purpose input 01 : rfu 10 : general-purpose output 11 : siu2 dtr2# output 13, 12 gp6md(1:0) these bits control direction and function of the gpio6 pin as follows: 00 : general-purpose input 01 : rfu 10 : general-purpose output 11 : siu2 rts2# output 11, 10 gp5md(1:0) these bits control direction and function of the gpio5 pin as follows: 00 : general-purpose input 01 : siu2 dcd2# input 10 : general-purpose output 11 : rfu 9, 8 gp4md(1:0) these bits control direction and function of the gpio4 pin as follows: 00 : general-purpose input 01 : rfu 10 : general-purpose output 11 : rfu 7, 6 gp3md(1:0) these bits control direction and function of the gpio3 pin as follows: 00 : general-purpose input 01 : rfu 10 : general-purpose output 11 : programmable chip select 0 output note holds the value before reset chapter 13 general purpose i/o unit (giu) user ? s manual u14272ej3v0um 247 (2/2) bit name function 5, 4 gp2md(1:0) these bits control direction and function of the gpio2 pin as follows: 00 : general-purpose input 01 : csi sck input 10 : general-purpose output 11 : rfu 3, 2 gp1md(1:0) these bits control direction and function of the gpio1 pin as follows: 00 : general-purpose input 01 : rfu 10 : general-purpose output 11 : csi so output 1, 0 gp0md(1:0) these bits control direction and function of the gpio0 pin as follows: 00 : general-purpose input 01 : csi si input 10 : general-purpose output 11 : rfu chapter 13 general purpose i/o unit (giu) user ? s manual u14272ej3v0um 248 13.3.2 gpmd1reg (0x0b00 0302) (1/2) bit 151413121110 9 8 name gp15md1 gp15md0 gp14md1 gp14md0 gp13md1 gp13md0 gp12md1 gp12md0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit 76543210 name gp11md1 gp11md0 gp10md1 gp10md0 gp9md1 gp9md0 gp8md1 gp8md0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit name function 15, 14 gp15md(1:0) these bits control direction and function of the gpio15 pin as follows: 00 : general-purpose input 01 : cd2# input 10 : general-purpose output 11 : color lcd fpd7 output 13, 12 gp14md(1:0) these bits control direction and function of the gpio14 pin as follows: 00 : general-purpose input 01 : cd1# input 10 : general-purpose output 11 : color lcd fpd6 output 11, 10 gp13md(1:0) these bits control direction and function of the gpio13 pin as follows: 00 : general-purpose input 01 : rfu 10 : general-purpose output 11 : color lcd fpd5 output 9, 8 gp12md(1:0) these bits control direction and function of the gpio12 pin as follows: 00 : general-purpose input 01 : rfu 10 : general-purpose output 11 : color lcd fpd4 output 7, 6 gp11md(1:0) these bits control direction and function of the gpio11 pin as follows: 00 : general-purpose input 01 : rfu 10 : general-purpose output 11 : programmable chip select 1 output note holds the value before reset remark when gpio15 and gpio14 pins are not defined as cd2# and cd1# signals respectively, the corresponding internal card detect signals to compactflash controller (ecu) are held to low level (active). chapter 13 general purpose i/o unit (giu) user ? s manual u14272ej3v0um 249 (2/2) bit name function 5, 4 gp10md(1:0) these bits control direction and function of the gpio10 pin as follows: 00 : general-purpose input 01 : csi frm input 10 : general-purpose output 11 : sysclk output 3, 2 gp9md(1:0) these bits control direction and function of the gpio9 pin as follows: 00 : general-purpose input 01 : siu2 cts2# input 10 : general-purpose output 11 : rfu 1, 0 gp8md(1:0) these bits control direction and function of the gpio8 pin as follows: 00 : general-purpose input 01 : siu2 dsr2# input 10 : general-purpose output 11 : rfu chapter 13 general purpose i/o unit (giu) user ? s manual u14272ej3v0um 250 13.3.3 gpmd2reg (0x0b00 0304) (1/2) bit 151413121110 9 8 name gp23md1 gp23md0 gp22md1 gp22md0 gp21md1 gp21md0 gp20md1 gp20md0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit 76543210 name gp19md1 gp19md0 gp18md1 gp18md0 gp17md1 gp17md0 gp16md1 gp16md0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit name function 15, 14 gp23md(1:0) these bits control direction and function of the gpio23 pin as follows: 00 : general-purpose input 01 : rfu 10 : general-purpose output 11 : romcs1# output 13, 12 gp22md(1:0) these bits control direction and function of the gpio22 pin as follows: 00 : general-purpose input 01 : rfu 10 : general-purpose output 11 : romcs0# output 11, 10 gp21md(1:0) these bits control direction and function of the gpio21 pin as follows: 00 : general-purpose input 01 : rfu 10 : general-purpose output 11 : reset# output 9, 8 gp20md(1:0) these bits control direction and function of the gpio20 pin as follows: 00 : general-purpose input 01 : rfu 10 : lcd m output 11 : ube# output 7, 6 gp19md(1:0) these bits control direction and function of the gpio19 pin as follows: 00 : general-purpose input 01 : iocs16# input 10 : general-purpose output 11 : rfu note holds the value before reset caution lcd m output can not be used in the v r 4181 of rev.1.0. chapter 13 general purpose i/o unit (giu) user ? s manual u14272ej3v0um 251 (2/2) bit name function 5, 4 gp18md(1:0) these bits control direction and function of the gpio18 pin as follows: 00 : general-purpose input 01 : iordy input 10 : general-purpose output 11 : rfu 3, 2 gp17md(1:0) these bits control direction and function of the gpio17 pin as follows: 00 : general-purpose input 01 : rfu 10 : general-purpose output 11 : iowr# output 1, 0 gp16md(1:0) these bits control direction and function of the gpio16 pin as follows: 00 : general-purpose input 01 : rfu 10 : general-purpose output 11 : iord# output chapter 13 general purpose i/o unit (giu) user ? s manual u14272ej3v0um 252 13.3.4 gpmd3reg (0x0b00 0306) (1/2) bit 151413121110 9 8 name gp31md1 gp31md0 gp30md1 gp30md0 gp29md1 gp29md0 gp28md1 gp28md0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit 76543210 name gp27md1 gp27md0 gp26md1 gp26md0 gp25md1 gp25md0 gp24md1 gp24md0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit name function 15, 14 gp31md(1:0) these bits control direction and function of the gpio31 pin as follows: 00 : general-purpose input 01 : siu1 dsr1# input 10 : general-purpose output 11 : rfu 13, 12 gp30md(1:0) these bits control direction and function of the gpio30 pin as follows: 00 : general-purpose input 01 : rfu 10 : general-purpose output 11 : siu1 dtr1# output 11, 10 gp29md(1:0) these bits control direction and function of the gpio29 pin as follows: 00 : general-purpose input 01 : siu1 dcd1# input 10 : general-purpose output 11 : rfu 9, 8 gp28md(1:0) these bits control direction and function of the gpio28 pin as follows: 00 : general-purpose input 01 : siu1 cts1# input 10 : general-purpose output 11 : rfu 7, 6 gp27md(1:0) these bits control direction and function of the gpio27 pin as follows: 00 : general-purpose input 01 : rfu 10 : general-purpose output 11 : siu1 rts1# output note holds the value before reset chapter 13 general purpose i/o unit (giu) user ? s manual u14272ej3v0um 253 (2/2) bit name function 5, 4 gp26md(1:0) these bits control direction and function of the gpio26 pin as follows: 00 : general-purpose input 01 : rfu 10 : general-purpose output 11 : siu1 txd1 output 3, 2 gp25md(1:0) these bits control direction and function of the gpio25 pin as follows: 00 : general-purpose input 01 : siu1 rxd1 input 10 : general-purpose output 11 : rfu 1, 0 gp24md(1:0) these bits control direction and function of the gpio24 pin as follows: 00 : general-purpose input 01 : rfu 10 : general-purpose output 11 : romcs2# output chapter 13 general purpose i/o unit (giu) user ? s manual u14272ej3v0um 254 13.3.5 gpdathreg (0x0b00 0308) bit 151413121110 9 8 name gpdat31 gpdat30 gpdat29 gpdat28 gpdat27 gpdat26 gpdat25 gpdat24 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit 76543210 name gpdat23 gpdat22 gpdat21 gpdat20 gpdat19 gpdat18 gpdat17 gpdat16 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit name function 15 to 0 gpdat(31:16) general-purpose data. there is a one-to-one correspondence between these bits and gpio pins. when a gpio pin is configured as a general-purpose input, the value of the pin can be read from this register. when the pin is defined as a general-purpose output, the value written to this register appears on the gpio pin. when one of the gpio(31:16) pins is configured as other function, the corresponding bit value in this register is invalid. note holds the value before reset chapter 13 general purpose i/o unit (giu) user ? s manual u14272ej3v0um 255 13.3.6 gpdatlreg (0x0b00 030a) bit 151413121110 9 8 name gpdat15 gpdat14 gpdat13 gpdat12 gpdat11 gpdat10 gpdat9 gpdat8 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit 76543210 name gpdat7 gpdat6 gpdat5 gpdat4 gpdat3 gpdat2 gpdat1 gpdat0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit name function 15 to 0 gpdat(15:0) general-purpose data. there is a one-to-one correspondence between these bits and gpio pins. when a gpio pin is configured as a general-purpose input, the value of the pin can be read from this register. when the pin is defined as a general-purpose output, the value written to this register appears on the gpio pin. when one of the gpio(15:0) pins is configured as other function, the corresponding bit value in this register is invalid. note holds the value before reset chapter 13 general purpose i/o unit (giu) user ? s manual u14272ej3v0um 256 13.3.7 gpinten (0x0b00 030c) bit 151413121110 9 8 name gien15 gien14 gien13 gien12 gien11 gien10 gien9 gien8 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit 76543210 name gien7 gien6 gien5 gien4 gien3 gien2 gien1 gien0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit name function 15 to 0 gien(15:0) gpio interrupt enable. there is a one-to-one correspondence between these bits and gpio pins. when one of the gpio(15:0) pins is defined as a general-purpose input, the corresponding bit in this register enables interrupts for that pin as follows: 0 : interrupt disabled 1 : interrupt enabled note holds the value before reset remark about the relationship between the gpinten and gpintmsk registers, refer to figure 13-1. gpio(15:0) interrupt request detecting logic . chapter 13 general purpose i/o unit (giu) user ? s manual u14272ej3v0um 257 13.3.8 gpintmsk (0x0b00 030e) bit 151413121110 9 8 name gimsk15 gimsk14 gimsk13 gimsk12 gimsk11 gimsk10 gimsk9 gimsk8 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 1 1 1 1 1 1 1 1 other resets note note note note note note note note bit 76543210 name gimsk7 gimsk6 gimsk5 gimsk4 gimsk3 gimsk2 gimsk1 gimsk0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 1 1 1 1 1 1 1 1 other resets note note note note note note note note bit name function 15 to 0 gimsk(15:0) gpio interrupt mask. there is a one-to-one correspondence between these bits and gpio pins. when a gpio pin is defined as a general-purpose input and interrupts is enabled on that pin, the interrupt can be temporarily masked by setting the corresponding bit in this register as follows: 0 : interrupt unmasked 1 : interrupt masked note holds the value before reset remark about the relationship between the gpinten and gpintmsk registers, refer to figure 13-1. gpio(15:0) interrupt request detecting logic . chapter 13 general purpose i/o unit (giu) user ? s manual u14272ej3v0um 258 13.3.9 gpinttyph (0x0b00 0310) (1/2) bit 151413121110 9 8 name i15typ1 i15typ0 i14typ1 i14typ0 i13typ1 i13typ0 i12typ1 i12typ0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit 76543210 name i11typ1 i11typ0 i10typ1 i10typ0 i9typ1 i9typ0 i8typ1 i8typ0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit name function 15, 14 i15typ(1:0) these bits define the type of interrupt generated when the gpio15 pin is defined as a general-purpose input: 00 : negative edge triggered interrupt 01 : positive edge triggered interrupt 10 : low level triggered interrupt 11 : high level triggered interrupt 13, 12 i14typ(1:0) these bits define the type of interrupt generated when the gpio14 pin is defined as a general-purpose input: 00 : negative edge triggered interrupt 01 : positive edge triggered interrupt 10 : low level triggered interrupt 11 : high level triggered interrupt 11, 10 i13typ(1:0) these bits define the type of interrupt generated when the gpio13 pin is defined as a general-purpose input: 00 : negative edge triggered interrupt 01 : positive edge triggered interrupt 10 : low level triggered interrupt 11 : high level triggered interrupt 9, 8 i12typ(1:0) these bits define the type of interrupt generated when the gpio12 pin is defined as a general-purpose input: 00 : negative edge triggered interrupt 01 : positive edge triggered interrupt 10 : low level triggered interrupt 11 : high level triggered interrupt note holds the value before reset chapter 13 general purpose i/o unit (giu) user ? s manual u14272ej3v0um 259 (2/2) bit name function 7, 6 i11typ(1:0) these bits define the type of interrupt generated when the gpio11 pin is defined as a general-purpose input: 00 : negative edge triggered interrupt 01 : positive edge triggered interrupt 10 : low level triggered interrupt 11 : high level triggered interrupt 5, 4 i10typ(1:0) these bits define the type of interrupt generated when the gpio10 pin is defined as a general-purpose input: 00 : negative edge triggered interrupt 01 : positive edge triggered interrupt 10 : low level triggered interrupt 11 : high level triggered interrupt 3, 2 i9typ(1:0) these bits define the type of interrupt generated when the gpio9 pin is defined as a general-purpose input: 00 : negative edge triggered interrupt 01 : positive edge triggered interrupt 10 : low level triggered interrupt 11 : high level triggered interrupt 1, 0 i8typ(1:0) these bits define the type of interrupt generated when the gpio8 pin is defined as a general-purpose input: 00 : negative edge triggered interrupt 01 : positive edge triggered interrupt 10 : low level triggered interrupt 11 : high level triggered interrupt chapter 13 general purpose i/o unit (giu) user ? s manual u14272ej3v0um 260 13.3.10 gpinttypl (0x0b00 0312) (1/2) bit 151413121110 9 8 name i7typ1 i7typ0 i6typ1 i6typ0 i5typ1 i5typ0 i4typ1 i4typ0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit 76543210 name i3typ1 i3typ0 i2typ1 i2typ0 i1typ1 i1typ0 i0typ1 i0typ0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit name function 15, 14 i7typ(1:0) these bits define the type of interrupt generated when the gpio7 pin is defined as a general-purpose input: 00 : negative edge triggered interrupt 01 : positive edge triggered interrupt 10 : low level triggered interrupt 11 : high level triggered interrupt 13, 12 i6typ(1:0) these bits define the type of interrupt generated when the gpio6 pin is defined as a general-purpose input: 00 : negative edge triggered interrupt 01 : positive edge triggered interrupt 10 : low level triggered interrupt 11 : high level triggered interrupt 11, 10 i5typ(1:0) these bits define the type of interrupt generated when the gpio5 pin is defined as a general-purpose input: 00 : negative edge triggered interrupt 01 : positive edge triggered interrupt 10 : low level triggered interrupt 11 : high level triggered interrupt 9, 8 i4typ(1:0) these bits define the type of interrupt generated when the gpio4 pin is defined as a general-purpose input: 00 : negative edge triggered interrupt 01 : positive edge triggered interrupt 10 : low level triggered interrupt 11 : high level triggered interrupt note holds the value before reset chapter 13 general purpose i/o unit (giu) user ? s manual u14272ej3v0um 261 (2/2) bit name function 7, 6 i3typ(1:0) these bits define the type of interrupt generated when the gpio3 pin is defined as a general-purpose input: 00 : negative edge triggered interrupt 01 : positive edge triggered interrupt 10 : low level triggered interrupt 11 : high level triggered interrupt 5, 4 i2typ(1:0) these bits define the type of interrupt generated when the gpio2 pin is defined as a general-purpose input: 00 : negative edge triggered interrupt 01 : positive edge triggered interrupt 10 : low level triggered interrupt 11 : high level triggered interrupt 3, 2 i1typ(1:0) these bits define the type of interrupt generated when the gpio1 pin is defined as a general-purpose input: 00 : negative edge triggered interrupt 01 : positive edge triggered interrupt 10 : low level triggered interrupt 11 : high level triggered interrupt 1, 0 i0typ(1:0) these bits define the type of interrupt generated when the gpio0 pin is defined as a general-purpose input: 00 : negative edge triggered interrupt 01 : positive edge triggered interrupt 10 : low level triggered interrupt 11 : high level triggered interrupt chapter 13 general purpose i/o unit (giu) user ? s manual u14272ej3v0um 262 13.3.11 gpintstat (0x0b00 0314) bit 151413121110 9 8 name gists15 gists14 gists13 gists12 gists11 gists10 gists9 gists8 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit 76543210 name gists7 gists6 gists5 gists4 gists3 gists2 gists1 gists0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit name function 15 to 0 gists(15:0) gpio interrupt request status. there is a one-to-one correspondence between these bits and gpio pins. when a gpio pin is defined as a general-purpose input, these bits reflect the interrupt request status as follows: 0 : no interrupt request pending 1 : interrupt request pending note holds the value before reset interrupt request pending status is reflected regardless of the setting of the interrupt mask bits. therefore, the status of an interrupt request can be returned as pending when this register is read even though the interrupt is masked. when a gpio interrupt request is defined as an edge triggered type, the interrupt request is cleared by writing 1 to the corresponding bit of this register. for example, if gpio11 is defined as an edge triggered interrupt request input, an interrupt request generated by this pin would be cleared by writing 1 to the bit 11 of this register. chapter 13 general purpose i/o unit (giu) user ? s manual u14272ej3v0um 263 13.3.12 gphibsth (0x0b00 0316) bit 151413121110 9 8 name gphst31 gphst30 gphst29 gphst28 gphst27 gphst26 gphst25 gphst24 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit 76543210 name gphst23 gphst22 gphst21 gphst20 gphst19 gphst18 gphst17 gphst16 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit name function 15 to 0 gphst(31:16) gpio hibernate pin state control. there is a one-to-one correspondence between these bits and gpio pins. these bits determine the state of gpio(31:16) pins during hibernate mode as follows: 0 : output pin is in high impedance input pin is ignored during hibernate mode 1 : output pin remains actively driven input pin is monitored during hibernate mode note holds the value before reset caution gpio29 pin (dcd1#) can be input at high level and monitored during hibernate mode and therefore the gphst29 bit can be set to 1. the gphst bits for all other gpio pins configured as inputs should be reset to 0. chapter 13 general purpose i/o unit (giu) user ? s manual u14272ej3v0um 264 13.3.13 gphibstl (0x0b00 0318) bit 151413121110 9 8 name gphst15 gphst14 gphst13 gphst12 gphst11 gphst10 gphst9 gphst8 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit 76543210 name gphst7 gphst6 gphst5 gphst4 gphst3 gphst2 gphst1 gphst0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit name function 15 to 0 gphst(15:0) gpio hibernate pin state control. there is a one-to-one correspondence between these bits and gpio pins. these bits determine the state of gpio(15:0) pins during hibernate mode as follows: 0 : output pin is in high impedance input pin is ignored during hibernate mode 1 : output pin remains actively driven input pin is monitored during hibernate mode note holds the value before reset remark in order to support wake-up events on one of the gpio(15:0) pins, the associated gphst bit must be set to 1. chapter 13 general purpose i/o unit (giu) user ? s manual u14272ej3v0um 265 13.3.14 gpsictl (0x0b00 031a) (1/2) bit 151413121110 9 8 name loopbk1 reserved reserved reserved regrxd1 regcts1 regdsr1 reg dcd1 r/w r/w r r r r/w r/w r/w r/w rtcrst 0 0 0 0 1 1 1 1 other resets note 000 note note note note bit 76543210 name loopbk2 reserved reserved reserved reserved regcts2 regdsr2 reg dcd2 r/w r/w r r r r r/w r/w r/w rtcrst 0 0 0 0 0 1 1 1 other resets note 0000 note note note bit name function 15 loopbk1 loopback enable for serial interface channel 1. when gpio pins have not been allocated for the line status signals dsr1# and/or cts1# of the serial interface channel 1, this bit can be set to 1 to allow the serial interface line status output signals to be connected to the line status input signals as follows: dtr1# output from serial interface drives the dsr1# input to serial interface rts1# output from serial interface drives the cts1# input to serial interface 14 to 12 reserved 0 is returned when read 11 regrxd1 rxd1 data. when a gpio pin has not been enabled to provide rxd1, the rxd1 input to the serial interface channel 1 is driven with the value of this bit. 10 regcts1 cts1# data. when the loopbk1 bit is reset to 0 and a gpio pin has not been enabled to provide cts1#, the cts1# input to the serial interface channel 1 is driven with the value of this bit. 9 regdsr1 dsr1# data. when the loopbk1 bit is reset to 0 and a gpio pin has not been enabled to provide dsr1#, the dsr1# input to the serial interface channel 1 is driven with the value of this bit. 8 regdcd1 dcd1# data. when a gpio pin has not been enabled to provide dcd1#, the dcd1# input to the serial interface channel 1 is driven with the value of this bit. note holds the value before reset chapter 13 general purpose i/o unit (giu) user ? s manual u14272ej3v0um 266 (2/2) bit name function 7 loopbk2 loopback enable for serial interface channel 2. when gpio pins have not be allocated for the line status signals dsr2# and/or cts2# of the serial interface channel 2, this bit can be set to 1 to allow the serial interface line status output signals to be connected to the line status input signals as follows: dtr2# output from serial interface drives the dsr2# input to serial interface rts2# output from serial interface drives the cts2# input to serial interface 6 to 3 reserved 0 is returned when read 2 regcts2 cts2# data. when the loopbk2 bit is reset to 0 and a gpio pin has not been enabled to provide cts2#, the cts2# input to the serial interface channel 2 is driven with the value of this bit. 1 regdsr2 dsr2# data. when the loopbk2 bit is reset to 0 and a gpio pin has not been enabled to provide dsr2#, the dsr2# input to the serial interface channel 2 is driven with the value of this bit. 0 regdcd2 dcd2# data. when a gpio pin has not been enabled to provide dcd2#, the dcd2# input to the serial interface channel 2 is driven with the value of this bit. chapter 13 general purpose i/o unit (giu) user ? s manual u14272ej3v0um 267 13.3.15 keyen (0x0b00 031c) bit 151413121110 9 8 name keysel reserved reserved reserved reserved reserved reserved reserved r/w r/wrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets note 0000000 bit 76543210 name cfhiben reserved reserved reserved reserved reserved reserved reserved r/w r/wrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets note 0000000 bit name function 15 keysel keyboard scan pin enable. this bit causes the pins assigned to support the compactflash interface to be redefined to support the keyboard scan interface. 0 : compactflash interface enabled 1 : keyboard scan interface enabled 14 to 8 reserved 0 is returned when read 7 cfhiben compactflash interface enable during hibernate mode 0 : disable 1 : enable 6 to 0 reserved 0 is returned when read note holds the value before reset the giu only provides an internal output signal (keysel) when the keysel bit is set to 1. an external logic is responsible for multiplexing the pin inputs and pin outputs, and i/o buffer enable control from the ecu and the kiu. when the compactflash interface is enabled during hibernate mode, a high-to-low transition on the compactflash cf_busy# pin will cause the v r 4181 to wake up and return to fullspeed mode. chapter 13 general purpose i/o unit (giu) user ? s manual u14272ej3v0um 268 13.3.16 pcs0stra (0x0b00 0320) bit 151413121110 9 8 name pcs0stra 15 pcs0stra 14 pcs0stra 13 pcs0stra 12 pcs0stra 11 pcs0stra 10 pcs0stra 9 pcs0stra 8 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit 76543210 name pcs0stra 7 pcs0stra 6 pcs0stra 5 pcs0stra 4 pcs0stra 3 pcs0stra 2 pcs0stra 1 pcs0stra 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit name function 15 to 0 pcs0stra(15:0) programmable chip select 0 start address. these bits determine the starting address for the memory or i/o chip select. note holds the value before reset 13.3.17 pcs0stpa (0x0b00 0322) bit 151413121110 9 8 name pcs0stpa 15 pcs0stpa 14 pcs0stpa 13 pcs0stpa 12 pcs0stpa 11 pcs0stpa 10 pcs0stpa 9 pcs0stpa 8 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit 76543210 name pcs0stpa 7 pcs0stpa 6 pcs0stpa 5 pcs0stpa 4 pcs0stpa 3 pcs0stpa 2 pcs0stpa 1 pcs0stpa 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit name function 15 to 0 pcs0stpa(15:0) programmable chip select 0 stop address. these bits determine the ending address for the memory or i/o chip select. note holds the value before reset chapter 13 general purpose i/o unit (giu) user ? s manual u14272ej3v0um 269 13.3.18 pcs0hia (0x0b00 0324) bit 151413121110 9 8 name reserved reserved reserved reserved pcs0hia 27 pcs0hia 26 pcs0hia 25 pcs0hia 24 r/w r r r r r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets0000 note1 note1 note1 note1 bit 76543210 name pcs0hia 23 pcs0hia 22 pcs0hia 21 pcs0hia 20 pcs0hia 19 pcs0hia 18 pcs0hia 17 pcs0hia 16 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note1 note1 note1 note1 note1 note1 note1 note1 bit name function 15 to 12 reserved 0 is returned when read 11 to 0 pcs0hia(27:16) programmable chip select 0 high address. a programmable chip select 0 will be generated when all of the following conditions have been met: ? the system address bits a(15:0) are equal to or greater than pcs0stra(15:0) and equal to or less than pcs0stpa(15:0) note2 ? the internal address bits a(27:16) are equal to pcs0hia(27:16) ? the read/write qualifier conditions specified by the pcsmode register have been met. notes 1. holds the value before reset 2. when the pcs0 has been defined as a 16-bit chip select, bit 0 of the address is ignored. chapter 13 general purpose i/o unit (giu) user ? s manual u14272ej3v0um 270 13.3.19 pcs1stra (0x0b00 0326) bit 151413121110 9 8 name pcs1stra 15 pcs1stra 14 pcs1stra 13 pcs1stra 12 pcs1stra 11 pcs1stra 10 pcs1stra 9 pcs1stra 8 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit 76543210 name pcs1stra 7 pcs1stra 6 pcs1stra 5 pcs1stra 4 pcs1stra 3 pcs1stra 2 pcs1stra 1 pcs1stra 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit name function 15 to 0 pcs1stra(15:0) programmable chip select 1 start address. these bits determine the starting address for the memory or i/o chip select. note holds the value before reset 13.3.20 pcs1stpa (0x0b00 0328) bit 151413121110 9 8 name pcs1stpa 15 pcs1stpa 14 pcs1stpa 13 pcs1stpa 12 pcs1stpa 11 pcs1stpa 10 pcs1stpa 9 pcs1stpa 8 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit 76543210 name pcs1stpa 7 pcs1stpa 6 pcs1stpa 5 pcs1stpa 4 pcs1stpa 3 pcs1stpa 2 pcs1stpa 1 pcs1stpa 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit name function 15 to 0 pcs1stpa(15:0) programmable chip select 1 stop address. these bits determine the ending address for the memory or i/o chip select. note holds the value before reset chapter 13 general purpose i/o unit (giu) user ? s manual u14272ej3v0um 271 13.3.21 pcs1hia (0x0b00 032a) bit 151413121110 9 8 name reserved reserved reserved reserved pcs1hia 27 pcs1hia 26 pcs1hia 25 pcs1hia 24 r/w r r r r r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets0000 note1 note1 note1 note1 bit 76543210 name pcs1hia 23 pcs1hia 22 pcs1hia 21 pcs1hia 20 pcs1hia 19 pcs1hia 18 pcs1hia 17 pcs1hia 16 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note1 note1 note1 note1 note1 note1 note1 note1 bit name function 15 to 12 reserved 0 is returned when read 11 to 0 pcs1hia(27:16) programmable chip select 1 high address. a programmable chip select 1 will be generated when all of the following conditions have been met: ? the system address bits a(15:0) are equal to or greater than pcs1stra(15:0) and equal to or less than pcs1stpa(15:0) note2 ? the internal address bits a(27:16) are equal to pcs1hia(27:16) ? the read/write qualifier conditions specified by the pcsmode register have been met. notes 1. holds the value before reset 2. when the pcs1 has been defined as a 16-bit chip select, bit 0 of the address is ignored. chapter 13 general purpose i/o unit (giu) user ? s manual u14272ej3v0um 272 13.3.22 pcsmode (0x0b00 032c) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit 76543210 name pcs1miob pcs1dsize pcs1md1 pcs1md0 pcs0miob pcs0dsize pcs0md1 pcs0md0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit name function 15 to 8 reserved 0 is returned when read 7 pcs1miob programmable chip select 1 target cycle 0 : enabled only during i/o cycles 1 : enabled only during memory cycles 6 pcs1dsize programmable chip select 1 data size 0 : defined as an 8-bit device. during accesses to the address range specified for pcs1, 8-bit cycles will be generated unless memcs16# or iocs16# is asserted. 1 : defined as a 16-bit device. during accesses to the address range specified for pcs1 16-bit cycles will be generated. 5, 4 pcs1md(1:0) programmable chip select 1 mode 00 : disabled 01 : qualified also with i/o or memory read strobe 10 : qualified also with i/o or memory write strobe 11 : based on address decode only 3 pcs0miob programmable chip select 0 target cycle 0 : enabled only during i/o cycles 1 : enabled only during memory cycles 2 pcs0dsize programmable chip select 0 data size 0 : defined as an 8-bit device. during accesses to the address range specified for pcs0, 8-bit cycles will be generated unless memcs16# or iocs16# is asserted. 1 : defined as a 16-bit device. during accesses to the address range specified for pcs0 16-bit cycles will be generated. 1, 0 pcs0md(1:0) programmable chip select 0 mode 00 : disabled 01 : qualified also with i/o or memory read strobe 10 : qualified also with i/o or memory write strobe 11 : based on address decode only note holds the value before reset chapter 13 general purpose i/o unit (giu) user ? s manual u14272ej3v0um 273 13.3.23 lcdgpmode (0x0b00 032e) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 0 0 0 0 0 0 0 0 other resets00000000 bit 76543210 name lcdgpen reserved reserved reserved lcdcs1 lcdcs0 g pvpbias g pvplcd r/w r/w r r r r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note 000 note note note note bit name function 15 to 8 reserved 0 is returned when read 7 lcdgpen control unit of lcd interface signals 0 : controlled by internal lcd controller 1 : controlled by external lcd controller shclk ? lcdcs# loclk ? memcs16# vplcd ? driven by the gpvplcd bit of this register vpbias ? driven by the gpvpbias bit of this register 6 to 4 reserved 0 is returned when read 3, 2 lcdcs(1:0) external lcd controller frame buffer address select. these bits determine the address range that will cause the lcdcs# signal to be asserted. 00 : 0x130a 0000 to 0x130a ffff (64kb pc/at compatible address space) 01 : 0x133e 0000 to 0x133f ffff (128kb) 10 : 0x133c 0000 to 0x133f ffff (256kb) 11 : 0x1338 0000 to 0x133f ffff (512kb) 1 gpvpbias output control for vpbias pin. when the lcdgpen bit is set to 1, the vpbias pin is driven by the value of this bit. 0 gpvplcd output control for vplcd pin. when the lcdgpen bit is set to 1, the vplcd pin is driven by the value of this bit. note holds the value before reset chapter 13 general purpose i/o unit (giu) user ? s manual u14272ej3v0um 274 13.3.24 miscregn (0x0b00 0330 to 0x0b00 034e) remark n = 0 to 15 miscreg0 (0x0b00 0330) miscreg8 (0x0b00 0340) miscreg1 (0x0b00 0332) miscreg9 (0x0b00 0342) miscreg2 (0x0b00 0334) miscreg10 (0x0b00 0344) miscreg3 (0x0b00 0336) miscreg11 (0x0b00 0346) miscreg4 (0x0b00 0338) miscreg12 (0x0b00 0348) miscreg5 (0x0b00 033a) miscreg13 (0x0b00 034a) miscreg6 (0x0b00 033c) miscreg14 (0x0b00 034c) miscreg7 (0x0b00 033e) miscreg15 (0x0b00 034e) bit 151413121110 9 8 name miscnd15 miscnd14 miscnd13 miscnd12 miscnd11 miscnd10 miscnd9 miscnd8 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit 76543210 name miscnd7 miscnd6 miscnd5 miscnd4 miscnd3 miscnd2 miscnd1 miscnd0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst 0 0 0 0 0 0 0 0 other resets note note note note note note note note bit name function 15 to 0 miscnd(15:0) miscellaneous data note holds the value before reset remark n = 0 to 15 these registers are battery-backed, and its contents are retained even in hibernate mode. user?s manual u14272ej3v0um 275 chapter 14 touch panel interface unit (piu) 14.1 general the piu uses the on-chip a/d converter to detect the x and y coordinates of pen contact locations on a touch panel and to scan the general-purpose a/d input port. since the touch panel control circuit and the a/d converter (conversion precision: 10 bits) are both incorporated, the touch panel is connected directly to the v r 4181. the piu?s function, namely the detection of x and y coordinates, is performed partly by hardware and partly by software. hardware tasks: touch panel applied voltage control reception of coordinate data software task: processing of coordinate data based on data sampled by hardware features of the piu?s hardware tasks are described below. can be directly connected to touch panel with four-pin resistance layers (on-chip touch panel driver) interface for on-chip a/d converter voltage detection at three general-purpose a/d ports and one audio input port operation of a/d converter based on various settings and control of voltage applied to touch panel sampling of x-coordinate and y-coordinate data variable coordinate data sampling interval interrupt is triggered if pen touch occurs regardless of cpu operation mode (interrupts do not occur during hibernate mode) four dedicated buffers with up to two pages each for coordinate data four buffers for a/d port scan auto/manual options for coordinate data sampling start/stop control caution no clocks are supplied to the piu, a/d converter, and d/a converter in the initial state. when using the piu, set the mskpiupclk, mskadupclk, and mskadu18m bits of the cmuclkmsk register in the mba host bridge to 1 in advance so that clocks are supplied. chapter 14 touch panel interface unit (piu) user?s manual u14272ej3v0um 276 14.1.1 block diagrams figure 14-1. piu peripheral block diagram v r 4181 battery, etc. i/o buffer i/o buffer piu adc selector 4 aiu audioin adin2 adin1 adin0 tpy1 tpy0 tpx1 tpx0 touch panel 4 1 ? touch panel a set of four pins are located at the edges of the x-axis and y-axis resistance layers, and the two layers have high resistance when there is no pen contact and low resistance when there is a pen contact. the resistance between the two edges of the resistance layers is about 1 k ? . when a voltage is applied to both edges of the y-axis resistance layer, the voltage (v y1 and v y2 in the figure below) is measures at the x-axis resistance layer ? s pins to determine the y coordinate. similarly, when a voltage is applied to both edges of the x-axis resistance layer, the voltage (v x1 and v x2 in the figure below) is measures at the y-axis resistance layer ? s pins to determine the x coordinate. for greater precision, voltages are again measured after switching plus and minus of the voltage applied to the resistance layer ? s pins. the obtained data is stored into the piupbnmreg register (n = 0 or 1, m = 0 to 3). chapter 14 touch panel interface unit (piu) user ? s manual u14272ej3v0um 277 figure 14-2. coordinate detection equivalent circuits tpx0 pin tpx1 pin: 0 v tpx0 pin: 3 v v y1 v x1 tpy1 pin: 3 v (a) y-coordinate detection (b) x-coordinate detection tpy0 pin: 0 v tpy0 pin tpx1 pin: 3 v tpx0 pin: 0 v v x2 tpy0 pin tpx0 pin v y2 tpy1 pin: 0 v tpy0 pin: 3 v figure 14-3. internal block diagram of piu v r 4181 scan sequencer touch panel interface controller a/d converter general-purpose a/d ports, audio input port piu piu registers internal bus controller internal bus touch panel chapter 14 touch panel interface unit (piu) user ? s manual u14272ej3v0um 278 the piu includes three blocks: the internal bus controller, the scan sequencer, and the touch panel interface controller. internal bus controller the internal bus controller controls the internal bus, the piu registers, and interrupts, and communicates with the a/d converter. scan sequencer the scan sequencer is used for piu state management. touch panel interface controller the touch panel interface controller is used to control the touch panel. 14.2 scan sequencer state transition figure 14-4. scan sequencer state transition diagram disable reset = 1 piupwr = 1 piuseqen = 1 & adpsstart = 1 piuseqen = 1 & padatstart = 1 release & padatstop = 1 piupwr = 0 adpsstart = 1 timeout piuseqen = 1 & padscanstart = 1 piuseqen = 0 or padscanstop = 1 auto standby piuseqen = 1 & piumode = 01 piuseqen = 0 waitpentouch adpscan adpsstart = 1 touch piuseqen = 0 datascan interval cmdscan release piuseqen = 0 chapter 14 touch panel interface unit (piu) user ? s manual u14272ej3v0um 279 disable state in this state, the a/d converter is in standby status, the output pins are in touch detection status (no piu interrupt), and the input pins are in mask status (to prevent misoperation when an undefined input is applied). standby state in this state, the piu is in scan idle status. the touch panel is in low-power status (0 v voltage is applied to the touch panel and the a/d converter is in disable status). normally, this is the state in which various mode settings are made. caution since a state transition occurs when the piuseqen bit is active, the piuseqen bit must be set as active after various mode settings have been completed. adpscan state this is the state in which voltage is measured at the a/d converter ? s three general-purpose ports and one audio input port. after the a/d converter is activated and voltage data is obtained, the data is stored in the piu ? s internal data buffer (piuabnreg, n = 0 to 3). after the four ports are scanned, an a/d port scan interrupt request occurs. after this interrupt occurs, the adpsstart bit is automatically set as inactive and the piu enters the state in which the adpsstart bit has been set as active. cmdscan state in this state, the a/d converter operates according to various settings. voltage data from one port only is fetched based on a combination of the touch panel pin setting (tpx(1:0), tpy(1:0)) and the selection of an input port (tpx(1:0), tpy(1:0), audioin, adin(2:0)) to the a/d converter. use piucmdreg register to make the touch panel pin setting and to select the input port. waitpentouch state this is a standby state in which the piu waits for a touch panel ? s ? touch ? status. when the piu detects a touch panel ? s ? touch ? status, a touch panel contact status change interrupt request occurs inside the piu. at this point, if the padatstart bit is active, the piu enters the datascan state. during the waitpentouch state, it is possible to enter suspend mode because the panel state can be detected even while the tclock is stopped. datascan state this is the state in which touch panel coordinates are detected. the a/d converter is activated and four data for each coordinate are sampled. caution if one complete set of coordinate data is not obtained during the interval between one set of coordinate data and the next coordinate data, a data lost interrupt request occurs. interval state this is the standby state in which the piu waits for the next coordinate sampling period or the touch panel ? s ? release ? status. after the touch panel status is detected, the time period specified via piusivlreg register elapses before the transition to the datascan state. if the piu detects the ? release ? status within the specified time period, a touch panel contact status change interrupt request occurs inside the piu. at this point, the piu enters the waitpentouch state if the padatstop bit is active. if the padatstop bit is inactive, it enters to the datascan state after the specified time period has elapsed. chapter 14 touch panel interface unit (piu) user ? s manual u14272ej3v0um 280 14.3 register set the piu registers are listed below. table 14-1. piu registers physical address r/w register symbol function 0x0b00 0122 r/w piucntreg piu control register 0x0b00 0124 r/w piuintreg piu interrupt cause register 0x0b00 0126 r/w piusivlreg piu data sampling interval register 0x0b00 0128 r/w piustblreg piu a/d converter start delay register 0x0b00 012a r/w piucmdreg piu a/d command register 0x0b00 0130 r/w piuascnreg piu a/d port scan register 0x0b00 0132 r/w piuamskreg piu a/d scan mask register 0x0b00 013e r piucivlreg piu data sampling period count register 0x0b00 02a0 r/w piupb00reg piu page 0 buffer 0 register 0x0b00 02a2 r/w piupb01reg piu page 0 buffer 1 register 0x0b00 02a4 r/w piupb02reg piu page 0 buffer 2 register 0x0b00 02a6 r/w piupb03reg piu page 0 buffer 3 register 0x0b00 02a8 r/w piupb10reg piu page 1 buffer 0 register 0x0b00 02aa r/w piupb11reg piu page 1 buffer 1 register 0x0b00 02ac r/w piupb12reg piu page 1 buffer 2 register 0x0b00 02ae r/w piupb13reg piu page 1 buffer 3 register 0x0b00 02b0 r/w piuab0reg piu a/d scan buffer 0 register 0x0b00 02b2 r/w piuab1reg piu a/d scan buffer 1 register 0x0b00 02b4 r/w piuab2reg piu a/d scan buffer 2 register 0x0b00 02b6 r/w piuab3reg piu a/d scan buffer 3 register 0x0b00 02bc r/w piupb04reg piu page 0 buffer 4 register 0x0b00 02be r/w piupb14reg piu page 1 buffer 4 register state of interrupt requests caused by the piu is indicated and can be set in the following registers, which are included in the icu (refer to chapter 9 interrupt control unit (icu) for details). table 14-2. piu interrupt registers physical address r/w register symbol function 0x0b00 0082 r piuintreg piu interrupt indication register 0x0b00 008e r/w mpiuintreg piu interrupt mask register chapter 14 touch panel interface unit (piu) user ? s manual u14272ej3v0um 281 14.3.1 piucntreg (0x0b00 0122) (1/2) bit 151413121110 9 8 name reserved reserved penstc padstate2 padstate1 padstate0 padatstop padatstart r/w r r r r r r r/w r/w rtcrst00000000 other resets00000000 bit 76543210 name padscan stop padscan start padscan type piumode1 piumode0 piuseqen piupwr padrst r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00000000 other resets00000000 bit name function 15, 14 reserved 0 is returned when read 13 penstc touch/release status when touch panel contact state changes 1 : touch 0 : release 12 to 10 padstate(2:0) scan sequencer status 111 : cmdscan 110 : interval 101 : datascan 100 : waitpentouch 011 : rfu 010 : adpscan 001 : standby 000 : disable 9 padatstop sequencer auto stop setting during touch panel release status 1 : auto stop after sampling data for one set of coordinates 0 : no auto stop 8 padatstart sequencer auto start setting during touch panel touch status 1 : auto start 0 : no auto start 7 padscanstop forced stop setting for touch panel sequencer 1 : forced stop after sampling data for one set of coordinates 0 : do not stop chapter 14 touch panel interface unit (piu) user ? s manual u14272ej3v0um 282 (2/2) bit name function 6 padscanstart start setting for touch panel sequencer 1 : forced start 0 : do not start 5 padscantype touch pressure sampling enable 1: enable 0: disable 4, 3 piumode(1:0) piu mode setting 11 : rfu 10 : rfu 01 : operates a/d converter using any command 00 : samples coordinate data 2 piuseqen scan sequencer operation enable 1 : enable 0 : disable 1 piupwr piu power mode setting 1 : sets piu output as active and puts into standby status 0 : sets panel to touch detection status and set piu operation stop enabled status 0 padrst piu reset. once the padrst bit is set to 1, it is automatically cleared to 0 after four tclock cycles. 1 : reset 0 : do not reset this register is used to make various settings for the piu. the penstc bit indicates the touch panel contact status at the time when the penchgintr bit of the piuintreg register is set to 1. this bit ? s state remains as it is until the penchgintr bit is cleared to 0. also, when the penchgintr bit is cleared to 0, the penstc bit indicates the touch panel contact status at that time. however, the penstc bit does not change while the penchgintr bit is set to 1, even if the touch panel contact status changes between release and touch. some bits in this register cannot be set in a specific state of scan sequencer. the combination of the setting of this register and the sequencer state is as follows. chapter 14 touch panel interface unit (piu) user ? s manual u14272ej3v0um 283 table 14-3. piucntreg bit manipulation and states piucntreg bit manipulation scan sequencer ? s state disable standby waitpentouch datascan padrst note1 0 1 ? disable disable disable piupwr 0 1 standby ? 1 0 ? disable piuseqen 0 1 waitpentouch ? ? 1 0 ? ? standby standby padatstart 0 1 ? datascan note2 1 0 ?? padatstop 0 1 ? 1 0 ? padscanstart 0 1 datascan note3 1 0 ? padscanstop 0 1 ? standby note4 1 0 ?? piucntreg bit manipulation scan sequencer ? s state interval adpscan cmdscan padrst note1 0 1 disable disable disable piupwr 0 1? ? ? 1 0 piuseqen 0 1? ? ? 1 0 standby standby standby padatstart 0 1 1 0 padatstop 0 1 1 0 padscanstart 0 1 1 0 padscanstop 0 1 standby note4 standby note4 standby note4 1 0? ?? after 1 is written, the bit is automatically cleared to 0 four tclock cycles later. 2. state transition occurs during touch status. 3. state transition occurs when the piuseqen bit is set to 1. 4. state transition occurs after one set of data is sampled. the padscanstop bit is cleared to 0 after the state transition occurs. remark ? : the bit change is retained but there is no state transition. : setting prohibited (operation not guaranteed) ? : combination of state and bit status before setting does not exist. chapter 14 touch panel interface unit (piu) user ? s manual u14272ej3v0um 284 14.3.2 piuintreg (0x0b00 0124) bit 151413121110 9 8 name ovp reserved reserved reserved reserved reserved reserved reserved r/w r/wrrrrrrr rtcrst00000000 other resets00000000 bit 76543210 name reserved padcmd intr padadp intr padpage1 intr padpage0 intr paddlost intr reserved penchg intr r/w r r/w r/w r/w r/w r/w r r/w rtcrst00000000 other resets00000000 bit name function 15 ovp valid page id bit (older valid page) 1 : page 1 retains an older valid data 0 : page 0 retains an older valid data 14 to 7 reserved 0 is returned when read 6 padcmdintr piu command scan interrupt request. this interrupt request occurs when a valid data is obtained during a command scan. cleared to 0 when 1 is written. 1 : occurred 0 : not occurred 5 padadpintr piu a/d port scan interrupt request. this interrupt request occurs when a set of valid data is obtained during an a/d port scan. cleared to 0 when 1 is written. 1 : occurred 0 : not occurred 4 padpage1intr piu data buffer page 1 interrupt request. this interrupt request occurs when a set of valid data is stored in the page 1 of the data buffer. cleared to 0 when 1 is written. 1 : occurred 0 : not occurred 3 padpage0intr piu data buffer page 0 interrupt request. this interrupt request occurs when a set of valid data is stored in the page 0 of the data buffer. cleared to 0 when 1 is written. 1 : occurred 0 : not occurred 2 paddlostintr data lost interrupt request. this interrupt request occurs when a set of data cannot be obtained during a specified time period. cleared to 0 when 1 is written. 1 : occurred 0 : not occurred 1 reserved 0 is returned when read 0 penchgintr touch panel contact status change interrupt request. cleared to 0 when 1 is written. 1 : occurred 0 : not occurred chapter 14 touch panel interface unit (piu) user ? s manual u14272ej3v0um 285 this register sets and indicates the interrupt request generation of the piu. when the penchgintr bit is set to1, the penstc bit of the piucntreg register indicates the touch panel contact status (touch or release) when a contact status changes. the penstc bit ? s status remains until the penchgintr bit is cleared to 0. also, when the penchgintr bit is cleared to 0, the penstc bit indicates the touch panel contact status. however, the penstc bit does not change while the penchgintr bit is set to 1, even if the touch panel contact status changes between release and touch. caution in the hibernate mode, the v r 4181 retains the touch panel status. therefore, if the hibernate mode has been entered while the touch panel is touched, the contact status may be mistakenly recognized as having changed, when the v r 4181 returns to fullspeed mode. if a touch panel status change interrupt request occurs immediately after the v r 4181 returns from the hibernate mode, the penchgintr bit may be set to 1 due to a miss-recognition such as above. similarly, other bits of the piuintreg register may be set to 1 on returning from the hibernate mode. therefore, set each bit of the piuintreg register to 1 to clear an interrupt request immediately after a restore from the hibernate mode. 14.3.3 piusivlreg (0x0b00 0126) bit 151413121110 9 8 name reserved reserved reserved reserved reserved scan intval10 scan intval9 scan intval8 r/w r r r r r r/w r/w r/w rtcrst00000000 other resets00000000 bit 76543210 name scan intval7 scan intval6 scan intval5 scan intval4 scan intval3 scan intval2 scan intval1 scan intval0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst10100111 other resets10100111 bit name function 15 to 11 reserved 0 is returned when read 10 to 0 scanintval(10:0) coordinate data scan sampling interval setting interval = scanintval(10:0) x 30 s this register sets the scan interval (sampling period) for coordinate data sampling. the sampling interval for one set of coordinate data is the value set via scanintval(10:0) multiplied by 30 s. accordingly, the logical range of sampling intervals that can be set in 30 s units is from 0 s to about 60 ms. actually, if the sampling interval setting is shorter than the time required for obtaining a set of coordinate data or adpscan data, a data lost interrupt request will occur. if data lost interrupt requests occur frequently, set a longer interval time. chapter 14 touch panel interface unit (piu) user ? s manual u14272ej3v0um 286 figure 14-5. interval times and states state operation datascan interval adpscan interval datascan s a s a s a s a interval time s t a a a a t s a s a s a s a remark s: voltage stabilization wait time (stable(5:0) in piustblreg) a: a/d converter conversion time (about 10 s) t: touch/release detection 14.3.4 piustblreg (0x0b00 0128) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst00000000 other resets00000000 bit 76543210 name reserved reserved stable5 stable4 stable3 stable2 stable1 stable0 r/w r r r/w r/w r/w r/w r/w r/w rtcrst00000111 other resets00000111 bit name function 15 to 6 reserved 0 is returned when read 5 to 0 stable(5:0) touch panel voltage stabilization wait time (datascan, cmdscan state) a/d scan timeout time (adpscan state) touch detection start wait time (disable, waitpentouch, interval state) wait time = stable(5:0) 30 s the voltage stabilization wait time for the power applied to the touch panel can be set via the stable(5:0) bits in 30 s units between 0 s and 1,890 s. chapter 14 touch panel interface unit (piu) user ? s manual u14272ej3v0um 287 14.3.5 piucmdreg (0x0b00 012a) (1/2) bit 151413121110 9 8 name reserved reserved reserved stableon tpyen1 tpyen0 tpxen1 tpxen0 r/w r r r r/w r/w r/w r/w r/w rtcrst00000000 other resets00000000 bit 76543210 name tpyd1 tpyd0 tpxd1 tpxd0 adcmd3 adcmd2 adcmd1 adcmd0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00001111 other resets00001111 bit name function 15 to 13 reserved 0 is returned when read 12 stableon touch panel voltage stabilization wait time (stable(5:0) of piustblreg) enable during command scan 1 : wait for panel voltage stabilization time 0 : ignore panel voltage stabilization time (wait time = 0) 11, 10 tpyen(1:0) tpy port input/output switching during command scan 11 : tpy1 output, tpy0 output 10 : tpy1 output, tpy0 input 01 : tpy1 input, tpy0 output 00 : tpy1 input, tpy0 input 9, 8 tpxen(1:0) tpx port input/output switching during command scan 11 : tpx1 output, tpx0 output 10 : tpx1 output, tpx0 input 01 : tpx1 input, tpx0 output 00 : tpx1 input, tpx0 input 7, 6 tpyd(1:0) tpy output level during command scan 11 : tpy1 = ? h ? , tpy0 = ? h ? 10 : tpy1 = ? h ? , tpy0 = ? l ? 01 : tpy1 = ? l ? , tpy0 = ? h ? 00 : tpy1 = ? l ? , tpy0 = ? l ? 5, 4 tpxd(1:0) tpx output level during command scan 11 : tpx1 = ? h ? , tpx0 = ? h ? 10 : tpx1 = ? h ? , tpx0 = ? l ? 01 : tpx1 = ? l ? , tpx0 = ? h ? 00 : tpx1 = ? l ? , tpx0 = ? l ? remark l: low level, h: high level chapter 14 touch panel interface unit (piu) user ? s manual u14272ej3v0um 288 (2/2) bit name function 3 to 0 adcmd(3:0) a/d converter input port selection for command scan 1111 : a/d converter standby mode request 1110 : rfu : 1000 : rfu 0111 : audioin port 0110 : adin2 port 0101 : adin1 port 0100 : adin0 port 0011 : tpy1 port 0010 : tpy0 port 0001 : tpx1 port 0000 : tpx0 port this register switches input/output and sets output level for each port during a command scanning operation. the setting of the tpyd bits are invalid when a port is set as input in the tpyen bits. the setting of the tpxd bits are invalid when a port is set as input in the tpxen bits. chapter 14 touch panel interface unit (piu) user ? s manual u14272ej3v0um 289 14.3.6 piuascnreg (0x0b00 0130) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst00000000 other resets00000000 bit 76543210 name reserved reserved reserved reserved reserved reserved tppscan adps start r/w r r r r r r r/w r/w rtcrst00000000 other resets00000000 bit name function 15 to 2 reserved 0 is returned when read 1 tppscan port selection for adpscan 1 : select tpx(1:0), tpy(1:0) (for touch panel) as a/d port 0 : select adin(2:0) (general-purpose) as a/d port and audioin as audio input port 0 adpsstart adpscan start 1 : start adpscan 0 : do not perform adpscan this register is used for adpscan setting. the adpscan begins when the adpsstart bit is set. after the adpscan is completed, the sequencer returns to the state when adpscan was started, and the adpsstart bit is cleared to 0 automatically. if the adpscan is not completed within the time period set via the stable bits of the piustblreg register, a data lost interrupt request occurs as a timeout interrupt. caution manipulation of the tppscan bit is valid only in the standby state. in the other states, the operation is not guaranteed. some bits in this register cannot be set in a specific state of scan sequencer. the combination of the setting of this register and the sequencer state is as follows. chapter 14 touch panel interface unit (piu) user ? s manual u14272ej3v0um 290 table 14-4. piuascnreg bit manipulation and states scan sequencer ? s state piuascnreg bit manipulation disable standby waitpentouch datascan adpsstart note1 0 1 adpscan note2 adpscan note2 1 0 ?? tppscan 0 1 ???? 1 0 ???? piucntreg bit manipulation scan sequencer ? s state interval adpscan cmdscan adpsstart note1 0 1 adpscan note2 adpscan note2 1 0? ? tppscan 0 1 1 0? immediately after a transition to the adpscan state, the bit is automatically cleared to 0. 2. after adpscan is completed, the sequencer returns to the state in which the scan has started. remark ? : the bit change is retained but there is no state transition. : setting prohibited (operation not guaranteed) ? : combination of state and bit status before setting does not exist. chapter 14 touch panel interface unit (piu) user ? s manual u14272ej3v0um 291 14.3.7 piuamskreg (0x0b00 0132) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst00000000 other resets00000000 bit 76543210 name adinm3 adinm2 adinm1 adinm0 tpym1 tpym0 tpxm1 tpxm0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00000000 other resets00000000 bit name function 15 to 8 reserved 0 is returned when read 7 adinm3 audio input port mask 1 : mask 0 : normal 6 to 4 adinm(2:0) general-purpose a/d port mask 1 : mask 0 : normal 3, 2 tpym(1:0) touch panel a/d port tpy mask 1 : mask 0 : normal 1, 0 tpxm(1:0) touch panel a/d port tpx mask 1 : mask 0 : normal this register is used to set masking each a/d port. each bit corresponds to one port. if masked, a/d conversions are not performed for data of the corresponding port. settings in this register are valid only during the adpscan state. chapter 14 touch panel interface unit (piu) user ? s manual u14272ej3v0um 292 14.3.8 piucivlreg (0x0b00 013e) bit 151413121110 9 8 name reserved reserved reserved reserved reserved check intval10 check intval9 check intval8 r/w rrrrrrrr rtcrst00000000 other resets00000000 bit 76543210 name check intval7 check intval6 check intval5 check intval4 check intval3 check intval2 check intval1 check intval0 r/w rrrrrrrr rtcrst10100000 other resets10100000 bit name function 15 to 11 reserved 0 is returned when read 10 to 0 checkintval(10:0) interval count value. this register indicates the value of an internal register that counts down based on the piusivlreg register setting. chapter 14 touch panel interface unit (piu) user ? s manual u14272ej3v0um 293 14.3.9 piupbnmreg (0x0b00 02a0 to 0x0b00 02ae, 0x0b00 02bc to 0x0b00 02be) remark n = 0, 1, m = 0 to 4 piupb00reg (0x0b00 02a0) piupb10reg (0x0b00 02a8) piupb01reg (0x0b00 02a2) piupb11reg (0x0b00 02aa) piupb02reg (0x0b00 02a4) piupb12reg (0x0b00 02ac) piupb03reg (0x0b00 02a6) piupb13reg (0x0b00 02ae) piupb04reg (0x0b00 02bc) piupb14reg (0x0b00 02be) bit 151413121110 9 8 name valid reserved reserved reserved reserved reserved paddata9 paddata8 r/w r/w r r r r r r/w r/w rtcrst00000000 other resets00000000 bit 76543210 name paddata7 paddata6 paddata5 paddata4 paddata3 paddata2 paddata1 paddata0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00000000 other resets00000000 bit name function 15 valid indicates validity of data in page buffer 1 : valid 0 : invalid 14 to 10 reserved 0 is returned when read 9 to 0 paddata(9:0) a/d converter ? s sampling data these registers are used to store coordinate data or touch pressure data. there are four coordinate data buffers and one touch pressure data buffer, each of which holds two pages of coordinate data or pressure data, and the addresses (register addresses) where the coordinate data or the pressure data is stored are fixed. read coordinate data or pressure data from the corresponding register in a valid page. the valid bit, which indicates whether the data is valid, is automatically rendered invalid when the page buffer interrupt source (the padpage0intr or padpage1intr bit in the piuintreg register) is cleared. table 14-5 shows correspondences between the sampled data and the register in which the sampled data is stored. table 14-5. detected data and page buffers detected data page0 buffer page1 buffer x ? piupb00reg piupb10reg x+ piupb01reg piupb11reg y ? piupb02reg piupb12reg y+ piupb03reg piupb13reg z (touch pressure) piupb04reg piupb14reg chapter 14 touch panel interface unit (piu) user ? s manual u14272ej3v0um 294 14.3.10 piuabnreg (0x0b00 02b0 to 0x0b00 02b6) remark n = 0 to 3 piuab0reg (0x0b00 02b0) piuab1reg (0x0b00 02b2) piuab2reg (0x0b00 02b4) piuab3reg (0x0b00 02b6) bit 151413121110 9 8 name valid reserved reserved reserved reserved reserved paddata9 paddata8 r/w r/w r r r r r r/w r/w rtcrst00000000 other resets00000000 bit 76543210 name paddata7 paddata6 paddata5 paddata4 paddata3 paddata2 paddata1 paddata0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00000000 other resets00000000 bit name function 15 valid indicates validity of data in buffer 1 : valid 0 : invalid 14 to 10 reserved 0 is returned when read 9 to 0 paddata(9:0) a/d converter ? s sampling data these registers are used to store sampling data of the general-purpose a/d port and audio input port or command scan data. there are four data buffers and the addresses (register address) where the data is stored are fixed. the valid bit, which indicates whether the data is valid, is automatically rendered invalid when the page buffer interrupt source (the padadpintr bit in the piuintreg register) is cleared. table 14-6 shows correspondences between the sampled data and the register in which the sampled data is stored. table 14-6. a/d ports and data buffers register during adpscan during cmdscan tppscan = 0 tppscan = 1 piuab0reg piuab1reg piuab2reg piuab3reg adin0 adin1 adin2 audioin tpx0 tpx1 tpy0 tpy1 cmdscan data ? ? ? chapter 14 touch panel interface unit (piu) user ? s manual u14272ej3v0um 295 14.4 state transition flow be sure to initialize the piu before scan sequencer operation. initialization via a reset sets particular values for the sequence interval, etc., which should be re-set to appropriate values. the following registers require initial settings. scanintval(10:0) bit of piusivlreg register stable(5:0) bit of piustblreg register interrupt mask cancellation settings are required for registers other than the piu registers. table 14-7. mask clear during scan sequencer operation setting unit register bit value interrupt mask clear icu msysint1reg mpiuintr 1 icu mpiuintreg bits 6 to 0 0x7f clock mask clear mba host bridge cmuclkmsk mskpiupclk 1 (1) transition flow for voltage detection at a/d general-purpose ports and audio input port standby, waitpentouch, or interval state <1> piuamskreg mask setting for a/d ports and audio input port <2> piuascnreg adpsstart = 1 adpscan state <3> piuascnreg adpsstart = 0 standby, waitpentouch, or interval state (2) transition flow for auto scan coordinate detection standby state <1> piucntreg piumode(1:0) = 00 padatstart = 1 padatstop = 1 <2> piucntreg piuseqen = 1 waitpentouch state chapter 14 touch panel interface unit (piu) user ? s manual u14272ej3v0um 296 (3) transition flow for manual scan coordinate detection disable state <1> piucntreg piupwr = 1 standby state <2> piucntreg piumode(1:0) = 00 padscanstart = 1 <3> piucntreg piuseqen = 1 datascan state (4) transition flow when entering suspend mode transition standby, waitpentouch, or interval state <1> piucntreg piuseqen = 0 standby state <2> piucntreg piupwr = 1 disable state (5) transition flow when returning from suspend mode disable state <1> piucntreg piupwr = 1 standby state <2> piucntreg piumode(1:0) = 00 padatstart = 1 padatstop = 1 <3> piucntreg piuseqen = 1 waitpentouch state touch detected datascan state (6) transition flow for command scan disable state <1> piucntreg piupwr = 1 standby state <2> piucntreg piumode(1:0) = 01 <3> piucntreg setting of touch panel pins, selection of input port <4> piucntreg piuseqen = 1 cmdscan state chapter 14 touch panel interface unit (piu) user ? s manual u14272ej3v0um 297 14.5 relationships among tpx, tpy, adin, and audioin pins and states state padstate(2:0) tpx(1:0) tpy(1:0) audioin, adin(2:0) piu disable (pen status detection) disable note hh d ? ???? low-power standby standby 00 00 ???? pen status detection waitpentouch/interval hh d ? ???? voltage detection at general-purpose ad0 port adpscan 00 00 ??? i voltage detection at general-purpose ad1 port adpscan 00 00 ?? i ? voltage detection at general-purpose ad2 port adpscan 00 00 ? i ?? voltage detection at audio input port adpscan 00 00 i ??? touch pressure detection (z) datascan hh d ? ???? tpy1=l, tpy0=h, tpx0=samp (x ? ) datascan ? ilh ???? tpy1=h, tpy0=l, tpx0=samp (x+) datascan ? ihl ???? tpx1=l, tpx0=h, tpy0=samp (y ? ) datascan lh ? i ???? tpx1=h, tpx0=l, tpy0=samp (y+) datascan hl ? i ???? the states of pins are not guaranteed if the padstate(2:0) immediately before the cpu ? s suspend or hibernate instruction execution is in a state other then the disable state. remarks 0 : low level input 1 : high level input l : low level output h : high level output l : a/d converter input d : touch interrupt request input (with a pull-down resistor) d : no touch interrupt request input (with a pull-down resistor) ? : don ? t care chapter 14 touch panel interface unit (piu) user ? s manual u14272ej3v0um 298 14.6 timing 14.6.1 touch/release detection timing touch/release detection is not determined via the a/d converter but the voltage level of the tpy1 pin. the following figure shows a timing of touch/release detection and coordinate detection. figure 14-6. touch/release detection timing state standby waitpentouch datascan interval tpy(1:0), tpx(1:0) (padscantype = 0) touch detected note y ? release detected note tpy(1:0), tpx(1:0) (padscantype = 1) touch detected note x+ release detected note x ? y+ x+ zy ? y+ x ? determined according to the status of the tpy1 signal as follows. high level ? touched low level ? released 14.6.2 a/d port scan timing during an a/d port scan, the four ports of a/d converter ? s input channel are sequentially scanned and the scanned data are stored in the data buffers dedicated to a/d port scanning. the following figure shows an a/d port scan timing diagram. figure 14-7. a/d port scan timing state xxx adpscan xxx audioin, adin(2:0) adpsstart bit (piuascnreg) adin0 adin1 adin2 audioin remark xxx: standby, waitpentouch, or interval chapter 14 touch panel interface unit (piu) user ? s manual u14272ej3v0um 299 14.7 data loss conditions the piu issues a data lost interrupt request when any of the following four conditions exist. 1. data for one coordinate has not been obtained within the interval period 2. the a/d port scan has not been completed within the time set via piustblreg register 3. transfer of the next coordinate data starts while valid data for both pages remains in the buffer 4. the next data transfer starts while there is valid data in the adpscan buffer once a data lost interrupt request occurs, the sequencer is forcibly changed to the standby state. the cause and response to each condition are as follows. (1) when data for one coordinate has not been obtained within the interval period cause this condition occurs when the aiu has exclusive use of the a/d converter and the piu is therefore unable to use the a/d converter. if this data loss condition occurs frequently, implement a countermeasure that temporarily prohibits the aiu ? s use of the a/d converter. response after clearing the data lost interrupt request by setting the paddlostintr bit to 1, set the padatstart bit or padscanstart bit of the piucntreg register to restart the coordinate detection operation. once the data lost interrupt request is cleared, the page in which the loss occurred becomes invalid. if the valid data prior to the data loss is needed, be sure to save the data that is being stored in the page buffer before clearing the data lost interrupt request. (2) when the a/d port scan has not been completed within the time set via piustblreg register cause same as cause of condition 1. response after clearing the data lost interrupt request by setting the paddlostintr bit to 1, set the adpsstart bit of the piuascnreg register to restart the a/d port scan operation. once the data lost interrupt request is cleared, the page in which the loss occurred becomes invalid. if the valid data prior to the data loss is needed, be sure to save the data that is being stored in the page buffer before clearing the data lost interrupt request. chapter 14 touch panel interface unit (piu) user ? s manual u14272ej3v0um 300 (3) when transfer of the next coordinate data starts while valid data for both pages remains in the buffer cause this condition is caused when the data buffer contains two pages of valid data (both the data buffer page 1 and data buffer page 0 interrupt requests have occurred) but the valid data has not been processed. if the a/d converter is used frequently, the time from when both pages become full until when the data loss occurs may be shorter than that of the normal operation. response in this case, valid data contained in the pages when the data lost interrupt request occurs is never overwritten. after two pages of valid data are processed, clear the three interrupt requests by writing 1 to the paddlostintr, padpage1intr, and padpage0intr bits in the piuintreg register. after clearing these interrupt requests, set the padatstart or padscanstart bit of the piucntreg register to restart the coordinate detection operation. (4) when the next data transfer starts while there is valid data in the adpscan buffer cause this condition is caused when valid data is not processed even while the adpscan buffer holds valid data (a/d port scan interrupt request occurrence). response in this case, valid data contained in the buffer when the data lost interrupt request occurs is never overwritten. after valid data in the buffer is processed, clear the two interrupt requests by writing 1 to the paddlostintr and padadpintr bits in the piuintreg register. after clearing these interrupt requests, set the adpsstart bit of the piuascnreg to restart the general- purpose a/d port scan operation. user?s manual u14272ej3v0um 301 chapter 15 audio interface unit (aiu) 15.1 general the aiu controls the analog output (speaker output) processing of the internal d/a converter and the analog input (microphone input) processing of the internal a/d converter. it is also used to make settings related to the a/d and d/a converters. the main functions of the aiu are as follows: ? holding the digital value converted by the internal a/d converter ? holding the digital value to be converted by the internal d/a converter ? separating data being converted by the a/d or d/a converter and transfer data by using double buffers ? linking the update of the double buffers and the generation of dma transfer requests with the data conversion rate caution no clocks are supplied to the aiu, a/d converter, and d/a converter in the initial state. when using the aiu, set the mskaiupclk, mskadupclk, and mskadu18m bits of the cmuclkmsk register in the mba host bridge to 1 in advance so that clocks are supplied. chapter 15 audio interface unit (aiu) user?s manual u14272ej3v0um 302 15.2 register set the aiu registers are listed below. table 15-1. aiu registers physical address r/w register symbol function 0x0b00 0160 r/w sdmadatreg speaker dma data register 0x0b00 0162 r/w mdmadatreg microphone dma data register 0x0b00 0164 r/w davref_setup d/a converter vref setup register 0x0b00 0166 r/w sodatreg speaker output data register 0x0b00 0168 r/w scntreg speaker output control register 0x0b00 016e r/w scnvc_end speaker sample rate control register 0x0b00 0170 r/w midatreg microphone input data register 0x0b00 0172 r/w mcntreg microphone input control register 0x0b00 0178 r/w dvalidreg data valid indication register 0x0b00 017a r/w seqreg sequencer enable register 0x0b00 017c r/w intreg interrupt register 0x0b00 017e r/w mcnvc_end microphone sample rate control register state of interrupt requests caused by aiu is indicated and can be set in the following registers, which are included in the icu (refer to chapter 9 interrupt control unit (icu) for details). table 15-2. aiu interrupt registers physical address r/w register symbol function 0x0b00 0084 r aiuintreg aiu interrupt indication register 0x0b00 0090 r/w maiuintreg aiu interrupt mask register chapter 15 audio interface unit (aiu) user?s manual u14272ej3v0um 303 15.2.1 sdmadatreg (0x0b00 0160) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved sdma9 sdma8 r/w r r r r r r r/w r/w rtcrst00000010 other resets00000010 bit 76543210 name sdma7 sdma6 sdma5 sdma4 sdma3 sdma2 sdma1 sdma0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00000000 other resets00000000 bit name function 15 to 10 reserved 0 is returned when read 9 to 0 sdma(9:0) speaker output dma data this register is used to store 10-bit dma data for speaker output. when sodatreg register is empty, the data is transferred to the sodatreg register. write is used for debugging and is enabled when the aiusen bit of the seqreg register is set to 1. this register is initialized (0x0200) by resetting the aiusen bit of the seqreg register to 0. chapter 15 audio interface unit (aiu) user?s manual u14272ej3v0um 304 15.2.2 mdmadatreg (0x0b00 0162) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved mdma9 mdma8 r/w r r r r r r r/w r/w rtcrst00000010 other resets00000010 bit 76543210 name mdma7 mdma6 mdma5 mdma4 mdma3 mdma2 mdma1 mdma0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00000000 other resets00000000 bit name function 15 to 10 reserved 0 is returned when read 9 to 0 mdma(9:0) microphone input dma data this register is used prior to dma transfer to store 10-bit data that has been converted by the a/d converter and stored in the midatreg register. write is used for debugging and is enabled when the aiumen bit of the seqreg register is set to 1. this register is initialized (0x0200) by resetting the aiumen bit of the seqreg register to 0. therefore, if the aiumen bit is set to 0 during dma transfer, invalid data may be transferred. chapter 15 audio interface unit (aiu) user?s manual u14272ej3v0um 305 15.2.3 davref_setup (0x0b00 0164) bit 151413121110 9 8 name davref15 davref14 davref13 davref12 davref11 davref10 davref9 davref8 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00000000 other resets00000000 bit 76543210 name davref7 davref6 davref5 davref4 davref3 davref2 davref1 davref0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst01111101 other resets01111101 bit name function 15 to 0 davref(15:0) d/a converter vref setup time. this register is used to select a vref setup time for the d/a converter. the following expression is used to calculate the value set to this register. davref(15:0) = 5 s pclk frequency for example, if the internal peripheral clock (pclk) frequency is 25 mhz, the davref(15:0) bits should be set to as follows; davref(15:0) = 5 10 ? 6 25 10 6 = 0x007d chapter 15 audio interface unit (aiu) user?s manual u14272ej3v0um 306 15.2.4 sodatreg (0x0b00 0166) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved sodat9 sodat8 r/w r r r r r r r/w r/w rtcrst00000010 other resets00000010 bit 76543210 name sodat7 sodat6 sodat5 sodat4 sodat3 sodat2 sodat1 sodat0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00000000 other resets00000000 bit name function 15 to 10 reserved 0 is returned when read 9 to 0 sodat(9:0) speaker output data this register is used to store 10-bit dma data for speaker output. data is received from the sdmadatreg register and is sent to the d/a converter. write is used for debugging and is enabled when the aiusen bit of the seqreg register is set to 1. this register is initialized (0x0200) by resetting the aiusen bit of the seqreg register to 0. chapter 15 audio interface unit (aiu) user?s manual u14272ej3v0um 307 15.2.5 scntreg (0x0b00 0168) bit 151413121110 9 8 name daenaiu reserved reserved reserved reserved reserved reserved reserved r/w r/wrrrrrrr rtcrst00000000 other resets00000000 bit 76543210 name reserved reserved reserved reserved sstate reserved sstopen reserved r/w rrrrrrr/wr rtcrst00000000 other resets00000000 bit name function 15 daenaiu enables d/a converter operation (vref connection). 1 : on 0 : off 14 to 4 reserved 0 is returned when read 3 sstate indicates speaker operation state. 1 : operating 0 : stopped 2 reserved 0 is returned when read 1 sstopen speaker output dma transfer page boundary interrupt 1 : stop dma request at 1-page boundary 0 : stop dma request at 2-page boundary 0 reserved 0 is returned when read this register is used to control the aiu?s speaker block. the daenaiu bit controls the connection of vdd_ad and vref input to ladder type resistors in the d/a converter. setting this bit to 0 (off) allows low power consumption when not using the d/a converter. when using the d/a converter, this bit must be set following the sequence described in 15.3 operation sequence . the content of the sstate bit is valid only when the aiusen bit of the seqreg register is set to 1. chapter 15 audio interface unit (aiu) user?s manual u14272ej3v0um 308 15.2.6 scnvc_end (0x0b00 016e) bit 151413121110 9 8 name scnvc15 scnvc14 scnvc13 scnvc12 scnvc11 scnvc10 scnvc9 scnvc8 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00001000 other resets00001000 bit 76543210 name scnvc7 scnvc6 scnvc5 scnvc4 scnvc3 scnvc2 scnvc1 scnvc0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst11011100 other resets11011100 bit name function 15 to 0 scnvc(15:0) speaker sample rate control this register is used to select a conversion rate for the d/a converter. the following expression is used to calculate the value set to this register. scnvc(15:0) = pclk frequency/sample rate for example, if the desired conversion rate is 8 ksps and internal peripheral clock (pclk) frequency is 25 mhz, scnvc(15:0) bits should be set to as follows; scnvc(15:0) = 25 10 6 /8 10 3 = 0x0c35 caution set this register to a value that determines the conversion rate as 50 ksps or less. chapter 15 audio interface unit (aiu) user?s manual u14272ej3v0um 309 15.2.7 midatreg (0x0b00 0170) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved midat9 midat8 r/w r r r r r r r/w r/w rtcrst00000010 other resets00000010 bit 76543210 name midat7 midat6 midat5 midat4 midat3 midat2 midat1 midat0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00000000 other resets00000000 bit name function 15 to 10 reserved 0 is returned when read 9 to 0 midat(9:0) microphone input data this register is used to store 10-bit speaker input data that has been converted by the a/d converter. data is sent to the mdmadatreg register and is received from the a/d converter. write is used for debugging and is enabled when the aiumen bit of the seqreg register is set to 1. this register is initialized (0x0200) by resetting the aiumen bit of the seqreg register to 0. chapter 15 audio interface unit (aiu) user?s manual u14272ej3v0um 310 15.2.8 mcntreg (0x0b00 0172) bit 151413121110 9 8 name adenaiu reserved reserved reserved reserved reserved reserved reserved r/w r/wrrrrrrr rtcrst00000000 other resets00000000 bit 76543210 name reserved reserved reserved reserved mstate reserved mstopen adreqaiu r/w rrrrrrr/wr rtcrst00000000 other resets00000000 bit name function 15 adenaiu enables a/d converter operation (vref connection). 1 : on 0 : off 14 to 4 reserved 0 is returned when read 3 mstate indicates microphone operation state 1 : operating 0 : stopped 2 reserved 0 is returned when read 1 mstopen microphone input dma transfer page boundary interrupt 1 : stop dma request at 1-page boundary 0 : stop dma request at 2-page boundary 0 adreqaiu request for use of a/d converter 1 : requesting 0 : no request this register is used to control the aiu?s microphone block. the adenaiu bit controls the connection of vdd_ad and vref input to ladder type resistors in the a/d converter. setting this bit to 0 (off) allows low power consumption when not using the a/d converter. when using the a/d converter, this bit must be set following the sequence described in 15.3 operation sequence . the content of the mstate bit is valid only when the aiumen bit of the seqreg register is set to 1. the aiu has priority when a conflict occurs with the piu in relation to a/d conversion requests. chapter 15 audio interface unit (aiu) user?s manual u14272ej3v0um 311 15.2.9 dvalidreg (0x0b00 0178) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst00000000 other resets00000000 bit 76543210 name reserved reserved reserved reserved sodatv sdmav midatv mdmav r/w r r r r r/w r/w r/w r/w rtcrst00000000 other resets00000000 bit name function 15 to 4 reserved 0 is returned when read 3 sodatv this indicates whether valid data has been stored in sodatreg. 1 : valid data exists 0 : no valid data 2 sdmav this indicates whether valid data has been stored in sdmadatreg. 1 : valid data exists 0 : no valid data 1 midatv this indicates whether valid data has been stored in midatreg. 1 : valid data exists 0 : no valid data 0 mdmav this indicates whether valid data has been stored in mdmadatreg. 1 : valid data exists 0 : no valid data this register indicates whether valid data has been stored in the sodatreg, sdmadatreg, midatreg, or mdmadatreg register. if data has been written directly to the sodatreg, sdmadatreg, midatreg, or mdmadatreg register via software, the bits in this register are not set so that 1 must be written via software. write is used for debugging and is enabled when the aiusen or aiumen bit of the seqreg register is set to 1. if the aiusen bit = 0 or aiumen bit = 0 in the seqreg register, then the sodatv bit = sdmav bit = 0 or midatv bit = mdmav bit = 0. chapter 15 audio interface unit (aiu) user?s manual u14272ej3v0um 312 15.2.10 seqreg (0x0b00 017a) bit 151413121110 9 8 name aiurst reserved reserved reserved reserved reserved reserved reserved r/w r/wrrrrrrr rtcrst00000000 other resets00000000 bit 76543210 name reserved reserved reserved aiumen reserved reserved reserved aiusen r/w r r r r/w r r r r/w rtcrst00000000 other resets00000000 bit name function 15 aiurst aiu reset via software 1 : reset 0 : normal 14 to 5 reserved 0 is returned when read 4 aiumen microphone block operation and dma enable 1 : enable 0 : disable 3 to 1 reserved 0 is returned when read 0 aiusen speaker block operation and dma enable 1 : enable 0 : disable this register is used to enable/disable the aiu?s operation. chapter 15 audio interface unit (aiu) user?s manual u14272ej3v0um 313 15.2.11 intreg (0x0b00 017c) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved midleintr mstintr r/w r r r r r r r/w r/w rtcrst00000000 other resets00000000 bit 76543210 name reserved reserved reserved reserved reserved reserved sidleintr reserved r/w rrrrrrr/wr rtcrst00000000 other resets00000000 bit name function 15 to 10 reserved 0 is returned when read 9 midleintr microphone idle interrupt request (receive data loss). cleared to 0 when 1 is written. 1 : occurred 0 : normal 8 mstintr microphone receive completion interrupt request. cleared to 0 when 1 is written. 1 : occurred 0 : normal 7 to 2 reserved 0 is returned when read 1 sidleintr speaker idle interrupt request (mute). cleared to 0 when 1 is written. 1 : occurred 0 : normal 0 reserved 0 is returned when read this register indicates occurrence of various interrupt request of the aiu. when data is received from the a/d converter, the midleintr bit is set if valid data still exists in the midatreg register (midatv bit = 1). in this case, the midatreg register is overwritten. the mstintr bit is set when data is received in the mdmadatreg register. when data is passed to the d/a converter, the sidleintr bit is set if there is no valid data in the sodatreg register (sodatv bit = 0). however, this interrupt request is valid only after aiusen bit = 1 in the sodatreg register, after which sodatv bit = 1 in the dvalidreg register. chapter 15 audio interface unit (aiu) user?s manual u14272ej3v0um 314 15.2.12 mcnvc_end (0x0b00 017e) bit 151413121110 9 8 name mcnvc15 mcnvc14 mcnvc13 mcnvc12 mcnvc11 mcnvc10 mcnvc9 mcnvc8 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00001000 other resets00001000 bit 76543210 name mcnvc7 mcnvc6 mcnvc5 mcnvc4 mcnvc3 mcnvc2 mcnvc1 mcnvc0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst11011100 other resets11011100 bit name function 15 to 0 mcnvc(15:0) microphone sample rate control. this register is used to select a conversion rate for the a/d converter. the following expression is used to calculate the value set to this register. mcnvc(15:0) = pclk frequency/sample rate for example, if the desired conversion rate is 11.025 ksps and internal peripheral clock (pclk) frequency is 25 mhz, the mcnvc(15:0) bits should be set to as follows; mcnvc(15:0) = 25 10 6 /11.025 10 3 = 0x08dc caution set this register to a value that determines the conversion rate as 50 ksps or less. chapter 15 audio interface unit (aiu) user?s manual u14272ej3v0um 315 15.3 operation sequence 15.3.1 output (speaker) 1. set conversion rate (0x0b00 016e: scnvc(15:0) = any value) 2. set d/a converter vref setup time (0x0b00 0164: any value to be dvaref(15:0)/pclk frequency = 5 s) 3. enable dma after setting dma address in dcu 4. set d/a converter?s vref to on (0x0b00 0168: daenaiu = 1) 5. wait for vref resistor stabilization time (about 5 s) (use the rtc counter) even if speaker power is set to on and speaker operation is enabled (aiusen = 1) without waiting for vref resistor stabilization time, speaker output starts after the period calculated with the formula below. 5 + 1/conversion rate (44.1, 22.05, 11.025, or 8) ( s) in this case, however, a noise may occur when speaker power is set to on. 6. set speaker power on via gpio. 7. enable speaker operation (0x0b00 017a: aiusen = 1) dma request receive acknowledge and dma data from dma 0x0b00 0178: sdmav = sodatv = 1 output 10-bit data (0x0b00 0166: sodat(9:0)) to d/a converter sodatv = 0, sdmav = 1 send sdmadatreg data to sodatreg. sodatv = 1, sdmav = 0 output dma request and store the data after the next into sdmadatreg. sodatv = 1, sdmav = 1 update data at each conversion timing interval (becomes sidleintr = 1 when dma delays and sodatv = 0 during conversion timing interval, and (mute) interrupt request occurs) dma page boundary interrupt request occurs at page boundary clear the page interrupt request to continue output. 8. disable speaker operation (0x0b00 017a: aiusen = 0) 9. set speaker power off via gpio. 10. set d/a converter?s vref to off (0x0b00 0168: daenaiu = 0) 11. disable dma in dcu figure 15-1. speaker output and audioout pin audioout v dd /2 time <1> <2> <3> <4> <5> <6> <7> <8><9><10> <11> chapter 15 audio interface unit (aiu) user ? s manual u14272ej3v0um 316 15.3.2 input (microphone) 1. set conversion rate (0x0b00 017e: mcnvc(15:0) = any value) 2. set d/a converter vref setup time (0x0b00 0164: any value to be dvaref(15:0)/pclk frequency = 5 s) 3. enable dma after setting dma address in dcu 4. set a/d converter ? s vref to on (0x0b00 0172: adenaiu = 1) microphone power can be set on and microphone operation can be enabled (aiumen = 1) without waiting for vref resistor stabilization time (about 5 s). however, in such a case, sampling starts after the period calculated with the formula below. 5 + 1/conversion rate (44.1, 22.05, 11.025, or 8) ( s) 5. set microphone power on via gpio. 6. enable microphone operation (0x0b00 017a: aiumen = 1) output a/d request to a/d converter acknowledge and 10-bit conversion data are returned from a/d converter. store data in midatreg. 0x0b00 0178: mdmav = 0, midatv = 1 transfer data from midatreg to mdmadatreg. mdmav = 1, midatv = 0 mstintr = 1 and an interrupt request (receive complete) occurs. issue dma request and store mdmadatreg data to memory. mdmav = 0, midatv = 0 issue an a/d request once per conversion timing interval and receive 10-bit data (becomes midleintr = 1 when dma delays and midatv = 1 during conversion timing interval, and (data loss) interrupt request occurs) dma page boundary interrupt request occurs at page boundary clear the page interrupt request to continue output. 7. disable microphone operation (0x0b00 017a: aiumen = 0) 8. set microphone power off via gpio. 9. set a/d converter ? s vref to off (0x0b00 0172: adenaiu = 0) 10. disable dma in dcu figure 15-2. audioin pin and microphone operation audioin sampling <1> to <3> <4> <5><6> <7> <8> <9> <10> time user?s manual u14272ej3v0um 317 chapter 16 keyboard interface unit (kiu) 16.1 general the keyboard interface unit (kiu) provides the interface between the v r 4181 and an external matrix type keyboard. this unit supports key matrix of 8 x 8. the interface to the keyboard consists of scanout (3-state output) and scanin (input) lines. the scanout lines are used to search the matrix for pressed keys. the scanin lines are used to sense key press events and are read after each scanout line being at low level to locate the pressed key. scanout and scanin lines are allocated by programming compactflash pins to support this function during the power-on. if those pins are set as for keyboard interface, compactflash interface cannot be used. 16.2 functional description when the keyboard is idle, the scanout lines are all driven to 0 volts and the scanin lines are pulled to v dd by external 4.7 k ? resistors. when any key in the matrix is pressed, at least one scanin input is driven as low and signals a key press event to the kiu. once the key press event has been detected, the kiu may be programmed to generate a key down interrupt request, and to begin scanning the keyboard automatically or to wait until software enables the scan operation. keyboard scanning is performed by sequentially driving one scanout line as low while the others remain high impedance, and reading the state of the scanin lines and storing into keyboard data registers inside the kiu. once the last scanout line has been driven as low and the scanin lines read the kiu may generate a keyboard data ready interrupt request to inform system software that one keyboard scan operation has been completed. the kiu repeats this scan process until no further keys have been detected or until software disables the scan operation. at this point the kiu enters to the keyboard idle state or key press wait state. chapter 16 keyboard interface unit (kiu) user?s manual u14272ej3v0um 318 the following table illustrates the relationship between these bits: table 16-1. settings of keyboard scan mode astop astart mstart mstop operation 0 0 0 0 scanning disabled x x x 1 scanning stopped 0 x 1 0 manual scan mode. scan operation starts as soon as a setting of the mstart bit is detected by the scan sequencer and stops when the mstop bit is set to 1. 1 x 1 0 manual scan with auto stop mode. scan operation starts as soon as a setting of the mstart bit is detected by the scan sequencer and stops when no valid keyboard data has been read for stprep(5:0) times of consecutive scan cycles. 0 1 0 0 auto scan with manual stop mode. scan operation starts as soon as a key press is detected by the scan sequencer and stops when the mstop bit is set to 1. 1 1 0 0 auto scan mode. scan operation starts as soon as a key press is detected by the scan sequencer and stops when no valid keyboard data has been read for stprep(5:0) times of consecutive scan cycles. 16.2.1 automatic keyboard scan mode (auto scan mode) automatic scan mode is enabled through the astart and astop bits of the kiuscanrep register. when the astart bit is set to 1, keyboard scanning starts automatically following a key down interrupt request. when the astop bit is set to 1, keyboard scanning stops automatically after no valid keyboard data (i.e. all scanin lines are high level) has been read for the number of scan cycles specified by the stprep(5:0) bits of the kiuscanrep register. 16.2.2 manual keyboard scan mode (manual scan mode) manual scan mode is enabled through the mstart and mstop bits of the kiuscanrep register. software initiates a keyboard scan operation by setting the mstart bit to 1 and terminates keyboard scanning by setting the mstop bit to 1. when software sets the mstop bit to 1, the kiu will complete the current scan operation before disabling the scan logic. 16.2.3 key press detection all scanin lines are sampled by the kiu on the rising edge of the 32.768 khz clock. when any scanin line is sampled as low during a period of time from a rising edge to a falling edge of the 32.768 khz clock, a key down interrupt request is generated. if the astart bit of the kiuscanrep register is set to 1 at this time, the kiu begins scanning the keyboard. chapter 16 keyboard interface unit (kiu) user?s manual u14272ej3v0um 319 16.2.4 scan operation scan operations are controlled by the t1cnt(4:0) and t3cnt(4:0) bits of the kiuwks register and the wintvl(9:0) bits of the kiuwki register. the following diagram illustrates the relationship of these register bits to the scan operation: figure 16-1. scanout signal output timing t1cnt(4:0) + 1 t3cnt(4:0) scanout0 (output) hi-z hi-z scanout1 (output) hi-z hi-z scanout2 (output) hi-z hi-z scanout3 (output) hi-z hi-z scanout4 (output) hi-z hi-z scanout5 (output) hi-z hi-z t3cnt(4:0) wintvl(9:0) scanout6 (output) hi-z hi-z scanout7 (output) hi-z hi-z hi-z hi-z the t1cnt(4:0) bits specify the keyboard settling time and is expressed in 32.768 khz clock cycles. following the low level of one of the scanout(7:0) pins, the kiu will wait for the time set in the t1cnt(4:0) bits before reading returned data to the scanin(7:0) pins. actually the scanout pins will be driven as low for (t1cnt(4:0) + 1) 32.768 khz clock cycles. the t3cnt(4:0) bits specify the delay from driving one scanout pin as high impedance to driving the next scanout pin as low and is also expressed in 32.768 khz clock cycles. when the scanoutn pin is driven as high impedance, the kiu will wait for the time set in the t3cnt(4:0) bits before driving the scanoutn+1 pin as low to allow the external pull-up resistors to return the scaninn pin as high (n = 0 to 6). the wintvl(9:0) bits specify the interval between one scan and another in 32.768 khz clock cycles. after the last scanout pin has been driven as high impedance and a time set in the t3cnt(4:0) bits has elapsed, the kiu will wait for the time set in the wintvl(9:0) bits before driving scanout0 as low to start the next scan sequence. chapter 16 keyboard interface unit (kiu) user ? s manual u14272ej3v0um 320 16.2.5 reading scanned data scanned data is read from the scanin(7:0) pins. when a scanout pin has been driven as low and the keyboard settling time specified by the t1cnt(4:0) bits has been elapsed, the kiu latches scanned data from the scanin pins and stores into one of the internal key data registers. 16.2.6 interrupts and status reporting the kiu provides scan status indication that may be polled by the cpu core and may also generate interrupt requests to request keyboard servicing. scan status indication is provided through the sstat(1:0) bits of the kiuscans register. these bits are decoded as follows: sstat1 sstat0 kiu scan sequencer status 0 0 stopped 0 1 waiting for key press 1 0 scanning (t1cnt or t3cnt) 1 1 during scan interval (wintvl) the kiu generates 3 types of maskable interrupt requests. kiu interrupt pending status is reported through the kdatlost, kdatrdy, and keydown bits of the kiuint register. all interrupt requests generated by the kiu should be considered asynchronous and must be externally qualified with tclock. the key data lost interrupt request (kdatlost bit) signals that a data from the scanin line written to the key data register corresponding to the scanout0 pin before the previous data value is read by the cpu core. this interrupt source can be masked through the mskkdatlost bit of the mkiuintreg register. the key data ready interrupt request (kdatrdy bit) signals one complete scan operation has been completed. this interrupt request is generated during a write of a data from the scanin line to the key data register corresponding to the last scanout pin. this interrupt request source can be masked through the mskkdatrdy bit of the mkiuintreg register. the key down interrupt request (keydown bit) signals a key press event has been detected. this interrupt request is generated in synchronization with the rising edge of the 32.768 khz clock when the keyboard interface is idle and any scanin pin is sampled as low during a period of time from a rising edge to a falling edge of the 32.768 khz clock. this interrupt request source can be masked through the mskkdownint bit of the mkiuintreg register. the mskkdatlost, mskkdatrdy, and mskkdownint bits only prevent interrupt requests from being generated on the kiuintr signal (internal). these mask bits do not disable interrupt request event detection nor do they disable interrupt status reporting in the kiuint register. chapter 16 keyboard interface unit (kiu) user ? s manual u14272ej3v0um 321 16.3 register set the kiu registers are listed below. table 16-2. kiu registers physical address r/w register symbol function 0x0b00 0180 r kiudat0 scan line 0 keyboard data register 0x0b00 0182 r kiudat1 scan line 1 keyboard data register 0x0b00 0184 r kiudat2 scan line 2 keyboard data register 0x0b00 0186 r kiudat3 scan line 3 keyboard data register 0x0b00 0188 r kiudat4 scan line 4 keyboard data register 0x0b00 018a r kiudat5 scan line 5 keyboard data register 0x0b00 018c r kiudat6 scan line 6 keyboard data register 0x0b00 018e r kiudat7 scan line 7 keyboard data register 0x0b00 0190 r/w kiuscanrep scan control register 0x0b00 0192 r kiuscans scan status register 0x0b00 0194 r/w kiuwks key scan stable time register 0x0b00 0196 r/w kiuwki key scan interval time register 0x0b00 0198 r/w kiuint interrupt register state of interrupt requests caused by kiu is indicated and can be set in the following registers, which are included in the icu (refer to chapter 9 interrupt control unit (icu) for details). table 16-3. kiu interrupt registers physical address r/w register symbol function 0x0b00 0086 r/w kiuintreg kiu interrupt indication register 0x0b00 0092 r/w mkiuintreg kiu interrupt mask register chapter 16 keyboard interface unit (kiu) user ? s manual u14272ej3v0um 322 16.3.1 kiudatn (0x0b00 0180 to 0x0b00 018e) remark n = 0 to 7 kiudat0 (0x0b00 0180) kiudat4 (0x0b00 0188) kiudat1 (0x0b00 0182) kiudat5 (0x0b00 018a) kiudat2 (0x0b00 0184) kiudat6 (0x0b00 018c) kiudat3 (0x0b00 0186) kiudat7 (0x0b00 018e) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst00000000 other resets00000000 bit 76543210 name retdat7 retdat6 retdat5 retdat4 retdat3 retdat2 retdat1 retdat0 r/w rrrrrrrr rtcrst00000000 other resets00000000 bit name function 15 to 8 reserved 0 is returned when read 7 to 0 retdat(7:0) scan data 1 : key is released 0 : key is pressed these registers reflect the state of the returned signals for the selected scanout pins. each register corresponds to one scanout pin as follows: scanout pin kiudat register scanout7 kiudat7 scanout6 kiudat6 scanout5 kiudat5 scanout4 kiudat4 scanout3 kiudat3 scanout2 kiudat2 scanout1 kiudat1 scanout0 kiudat0 chapter 16 keyboard interface unit (kiu) user ? s manual u14272ej3v0um 323 16.3.2 kiuscanrep (0x0b00 0190) bit 151413121110 9 8 name keyen reserved reserved reserved reserved reserved stprep5 stprep4 r/w r/wrrrrrr/wr/w rtcrst00000000 other resets00000000 bit 76543210 name stprep3 stprep2 stprep1 stprep0 mstop mstart astop astart r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00000000 other resets00000000 bit name function 15 keyen kiu enable. this bit enables a kiu operation. when this bit is set to 0, the scan sequencer and all interrupt requests are disabled. 1 : enable 0 : disable 14 to 10 reserved 0 is returned when read 9 to 4 stprep(5:0) scan sequencer stop count. these bits select the number of scan operation performed after all keys have been released (0xff is loaded to kiudat registers). 111111 : 63 times : 000001 : 1 time 000000 : 64 times 3 mstop scan stop (manual mode). this bit is sampled at the end of each scan operation and causes the scan sequencer to stop scanning when set to 1. 1 : stop 0 : operate 2 mstart manual scan start (manual mode). when this bit is set to 1, the scan sequencer starts scanning the keyboard. 1 : start 0 : stop 1 astop auto scan stop (auto mode). when this bit is set to 1, the scan sequencer stops scanning automatically when all keys have been released for the number of scan operation specified by the stprep(5:0) bits. 1 : auto stop 0 : manual stop 0 astart auto scan mode enable. when this bit is set to 1, the scan sequencer starts scanning automatically following a key press event. 1 : enable 0 : disable chapter 16 keyboard interface unit (kiu) user ? s manual u14272ej3v0um 324 16.3.3 kiuscans (0x0b00 0192) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst00000000 other resets00000000 bit 76543210 name reserved reserved reserved reserved reserved reserved sstat1 sstat0 r/w rrrrrrrr rtcrst00000000 other resets00000000 bit name function 15 to 2 reserved 0 is returned when read 1, 0 sstat(1:0) scan sequencer status 11 : during scan interval (wintvl) 10 : scanning (t1cnt or t3cnt) 01 : waiting for key press 00 : stopped chapter 16 keyboard interface unit (kiu) user ? s manual u14272ej3v0um 325 16.3.4 kiuwks (0x0b00 0194) bit 151413121110 9 8 name reserved t3cnt4 t3cnt3 t3cnt2 t3cnt1 t3cnt0 reserved reserved r/w r r/w r/w r/w r/w r/w r r rtcrst00000000 other resets00000000 bit 76543210 name reserved reserved reserved t1cnt4 t1cnt3 t1cnt2 t1cnt1 t1cnt0 r/w r r r r/w r/w r/w r/w r/w rtcrst00000000 other resets00000000 bit name function 15 reserved 0 is returned when read 14 to 10 t3cnt(4:0) scan idle time. these bit determine the wait time the scan sequencer waits following a deassertion of one scanout pin before an assertion of the next scanout pin. 11111 : 960 s : (t3cnt(4:0) + 1) x 30 s 00001 : 60 s 00000 : setting prohibited 9 to 5 reserved 0 is returned when read 4 to 0 t1cnt(4:0) scan data stabilization time. these bits determine the time the scan sequencer waits following an assertion of a scanout pin before return data is read. 11111 : 960 s : (t1cnt(4:0) + 1) x 30 s 00001 : 60 s 00000 : setting prohibited chapter 16 keyboard interface unit (kiu) user ? s manual u14272ej3v0um 326 16.3.5 kiuwki (0x0b00 0196) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved wintvl9 wintvl8 r/w rrrrrrr/wr/w rtcrst00000000 other resets00000000 bit 76543210 name wintvl7 wintvl6 wintvl5 wintvl4 wintvl3 wintvl2 wintvl1 wintvl0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00000000 other resets00000000 bit name function 15 to 10 reserved 0 is returned when read 9 to 0 wintvl(9:0) scan interval time. these bits determine the time the scan sequencer waits following completion of one scan operation before starting the next scan operation. 1111111111 : 30690 s : wintvl(9:0) x 30 s 0000000001 : 30 s 0000000000 : no wait chapter 16 keyboard interface unit (kiu) user ? s manual u14272ej3v0um 327 16.3.6 kiuint (0x0b00 0198) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst00000000 other resets00000000 bit d7d6d5d4d3d2d1d0 name reserved reserved reserved reserved reserved kdatlost kdatrdy keydown r/w r r r r r r/w r/w r/w rtcrst00000000 other resets00000000 bit name function 15 to 3 reserved 0 is returned when read 2 kdatlost key data lost interrupt request. this interrupt request occurs if the kiudat0 register is updated with the next key data prior to being read by the cpu core. 1 : occurred 0 : not occurred this bit is cleared by writing 1. 1 kdatrdy key data ready interrupt request. this interrupt request occurs when a set of scanning is completed and all the kiudat registers are updated. 1 : occurred 0 : not occurred this bit is cleared by writing 1. 0 keydown key down interrupt request. this interrupt request occurs when the kiu sequencer is idle and any of the scanin inputs has been sampled as low level. 1 : occurred 0 : not occurred this bit is cleared by writing 1. user?s manual u14272ej3v0um 328 chapter 17 compactflash controller (ecu) 17.1 general the v r 4181 provides an exca-compatible controller (ecu) supporting a single compactflash slot. the interface for this controller is shared with that of the keyboard interface unit. to use this interface for compactflash control, the keysel bit of the keyen register in the giu must be clear to 0. also, to use cf_busy# signal as an activation factor, the compactflash interface must be enabled during hibernate mode by writing 1 to the cfhiben bit of the keyen register. 17.2 register set summary this section provides details of the ecu registers. two of the ecu registers are located in the i/o addressing space. these registers, as well as the interrupt and configuration registers, are shown in the following table. table 17-1. ecu control registers physical address r/w register symbol function 0x0b00 08e0 r/w ecuindx index register (i/o space) 0x0b00 08e1 r/w ecudata data register (i/o space) 0x0b00 08f8 r intstatreg interrupt status register 0x0b00 08fa r/w intmskreg interrupt mask register 0x0b00 08fe r/w cfg_reg_1 configuration register 1 the remaining ecu registers listed below are all 8-bit width and accessed through the index register and the data register. chapter 17 compactflash controller (ecu) user?s manual u14272ej3v0um 329 table 17-2. ecu registers (1/2) index r/w register symbol function 0x0000 r id_rev_reg identification and revision register 0x0001 r if_stat_reg interface status register 0x0002 r/w pwrrsetdrv power and resetdrv control register 0x0003 r/w itgenctreg interrupt and general control register 0x0004 r/w cdstchgreg card status change register 0x0005 r/w crdstatreg card status change interrupt configuration register 0x0006 r/w adwinenreg address window enable register 0x0007 r/w ioctrl_reg i/o control register 0x0008 r/w ioadslb0reg i/o start address 0 low byte register 0x0009 r/w ioadshb0reg i/o start address 0 high byte register 0x000a r/w ioslb0reg i/o stop address 0 low byte register 0x000b r/w ioshb0reg i/o stop address 0 high byte register 0x000c r/w ioadslb1reg i/o start address 1 low byte register 0x000d r/w ioadshb1reg i/o start address 1 high byte register 0x000e r/w ioslb1reg i/o stop address 1 low byte register 0x000f r/w ioshb1reg i/o stop address 1 high byte register 0x0010 r/w sysmemsl0reg system memory 0 mapping start address low byte register 0x0011 r/w memwid0_reg system memory 0 mapping start address high byte register 0x0012 r/w sysmemel0reg system memory 0 mapping stop address low byte register 0x0013 r/w memsel0_reg system memory 0 mapping stop address high byte register 0x0014 r/w memoffl0reg card memory 0 offset address low byte register 0x0015 r/w memoffh0reg card memory 0 offset address high byte register 0x0016 r/w dtgenclreg card detect and general control register 0x0018 r/w sysmemsl1reg system memory 1 mapping start address low byte register 0x0019 r/w memwid1_reg system memory 1 mapping start address high byte register 0x001a r/w sysmemel1reg system memory 1 mapping stop address low byte register 0x001b r/w memsel1_reg system memory 1 mapping stop address high byte register 0x001c r/w memoffl1reg card memory 1 offset address low byte register 0x001d r/w memoffh1reg card memory 1 offset address high byte register 0x001e r/w gloctrlreg global control register 0x001f r voltsenreg card voltage sense register chapter 17 compactflash controller (ecu) user?s manual u14272ej3v0um 330 table 17-2. ecu registers (2/2) index r/w register symbol function 0x0020 r/w sysmemsl2reg system memory 2 mapping start address low byte register 0x0021 r/w memwid2_reg system memory 2 mapping start address high byte register 0x0022 r/w sysmemel2reg system memory 2 mapping stop address low byte register 0x0023 r/w memsel2_reg system memory 2 mapping stop address high byte register 0x0024 r/w memoffl2reg card memory 2 offset address low byte register 0x0025 r/w memoffh2reg card memory 2 offset address high byte register 0x0028 r/w sysmemsl3reg system memory 3 mapping start address low byte register 0x0029 r/w memwid3_reg system memory 3 mapping start address high byte register 0x002a r/w sysmemel3reg system memory 3 mapping stop address low byte register 0x002b r/w memsel3_reg system memory 3 mapping stop address high byte register 0x002c r/w memoffl3reg card memory 3 offset address low byte register 0x002d r/w memoffh3reg card memory 3 offset address high byte register 0x002f r/w voltselreg card voltage select register 0x0030 r/w sysmemsl4reg system memory 4 mapping start address low byte register 0x0031 r/w memwid4_reg system memory 4 mapping start address high byte register 0x0032 r/w sysmemel4reg system memory 4 mapping stop address low byte register 0x0033 r/w memsel4_reg system memory 4 mapping stop address high byte register 0x0034 r/w memoffl4reg card memory 4 offset address low byte register 0x0035 r/w memoffh4reg card memory 4 offset address high byte register chapter 17 compactflash controller (ecu) user?s manual u14272ej3v0um 331 17.3 ecu control registers 17.3.1 intstatreg (0x0b00 08f8) bit 151413121110 9 8 name irq15 irq14 reserved irq12 irq11 irq10 irq9 reserved r/w rrrrrrrr reset 00000000 bit 76543210 name irq7 reserved irq5 irq4 irq3 reserved reserved reserved r/w rrrrrrrr reset 00000000 bit name function 15, 14 irq(15:14) status of interrupt request 15 and 14 (internal) 0 : invalid 1 : valid 13 reserved 0 is returned when read 12 to 9 irq(12:9) status of interrupt request 12, 11, 10 and 9 (internal) 0 : invalid 1 : valid 8 reserved 0 is returned when read 7 irq7 status of interrupt request 7 (internal) 0 : invalid 1 : valid 6 reserved 0 is returned when read 5 to 3 irq(5:3) status of interrupt request 5, 4 and 3 (internal) 0 : invalid 1 : valid 2 to 0 reserved 0 is returned when read remark a single bit corresponds to each interrupt request. chapter 17 compactflash controller (ecu) user?s manual u14272ej3v0um 332 17.3.2 intmskreg (0x0b00 08fa) bit 151413121110 9 8 name imsk015 imsk014 reserved imsk012 imsk011 imsk010 imsk09 reserved r/w r/w r/w r r/w r/w r/w r/w r reset 00000000 bit 76543210 name imsk07 reserved imsk05 imsk04 imsk03 reserved reserved reserved r/w r/w r r/w r/w r/w r r r reset 00000000 bit name function 15, 14 imsk0(15:14) mask for interrupt request 15 and 14 (internal) 0 : unmask 1 : mask 13 reserved 0 is returned when read 12 to 9 imsk0(12:9) mask for interrupt request 12, 11, 10, and 9 (internal) 0 : unmask 1 : mask 8 reserved 0 is returned when read 7 imsk07 mask for interrupt request 7 (internal) 0 : unmask 1 : mask 6 reserved 0 is returned when read 5 to 3 imsk0(5:3) mask for interrupt request 5, 4 and 3 (internal) 0 : unmask 1 : mask 2 to 0 reserved 0 is returned when read remark a single bit corresponds to each interrupt request. chapter 17 compactflash controller (ecu) user?s manual u14272ej3v0um 333 figure 17-1. compactflash interrupt logic cdstchgreg (index 0x04) dmux dmux or and/ or sirq(3:0) (index 0x05) irqsel(3:0) (index 0x03) intstatreg (0x0b00 08f8) intmskreg (0x0b00 08fa) status change interrupt batdead/stschg# (cf_stschg#) ireq (cf_busy#) cd1#, cd2#/ swcdint bit rdy/bsy# (cf_busy#) irq3 irq4 irq15 irq3 irq4 irq15 irq3 irq4 irq15 irq3 irq4 irq15 imsk3 imsk4 imsk15 ecuint (to icu) : : : : : : : : : : remark all irq signals are ored together to generate ecuint after anded with imsk0n bits in the intmskreg register (n = 0 to 15). 17.3.3 cfg_reg_1 (0x0b00 08fe) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr reset 00000000 bit 76543210 name reserved reserved reserved reserved reserved reserved reserved wse r/w rrrrrrrr/w reset 00000001 bit name function 15 to 1 reserved 0 is returned when read 0 wse internal isa cycle 1 wait state insertion enable. this bit controls wait insertion when accessing the ecu registers. write 1 to this bit when write. 1 : enable chapter 17 compactflash controller (ecu) user ? s manual u14272ej3v0um 334 17.4 ecu registers 17.4.1 id_rev_reg (index: 0x00) bit 76543210 name iftyp1 iftyp0 reserved reserved rev3 rev2 rev1 rev0 r/w rrrrrrrr reset 10000011 bit name function 7, 6 iftyp(1:0) pcsc interface type these bits indicate 10 to reflect that both memory and i/o cards are supported. 5, 4 reserved 0 is returned when read 3 to 0 rev(3:0) revision level. 0011 is always displayed. chapter 17 compactflash controller (ecu) user ? s manual u14272ej3v0um 335 17.4.2 if_stat_reg (index: 0x01) bit 76543210 name reserved pwron rdy/bsy wp cd2 cd1 reserved bvd1 r/w rrrrrrrr reset 1 0 undefined undefined 1 1 0 undefined bit name function 7 reserved 1 is returned when read 6 pwron compactflash card power status 0 : off 1 : on 5 rdy/bsy compactflash card ready/busy status. this bit indicates the current status of rdy/bsy# (cf_busy#) signal from a compactflash card. 0 : busy 1 : ready 4 wp memory write protect switch status. this bit indicates the current status of wp (cf_iois16#) signal from a compactflash card. 0 : off 1 : on 3, 2 cd(2:1) complement of the values of cd1# and cd2# note 11: active (low level) 00 : inactive (high level) values other than above are not displayed. 1 reserved 0 is returned when read 0 bvd1 this bit indicates the current status of stschg# (cf_stschg#) signal from a compactflash card. note the card detect pins, cd1# and cd2#, alternate with gpio pins. when the gpio pins are not programmed as card detect input, the cd(2:1) bits of this register always return 11 (active). in this way, the compactflash interface can be used without the card detect pins. when the gpio pins are programmed as card detect, the cd(2:1) bits are reflected in actual status of the cd1# and cd2# pins. chapter 17 compactflash controller (ecu) user ? s manual u14272ej3v0um 336 17.4.3 pwrrsetdrv (index: 0x02) bit 76543210 name oe reserved reserved pwren reserved reserved reserved reserved r/w r/w r r r/w r r r/w r reset 00100000 bit name function 7 oe output enable. if this bit is cleared to 0, the compactflash interface outputs from the v r 4181 are driven to high impedance state and the cf_den# and cf_aen# outputs are driven as high. caution this bit should not be set until this register has been written to set the compactflash card power enable. 6 reserved 0 is returned when read 5 reserved 1 is returned when read 4 pwren card power enable 0 : disabled (vcc is 0 v) 1 : enabled. voltage selected in the voltselreg register (0x2f) is applied. the power to the socked is turned on when a card is inserted and off when removed. caution the v r 4181 supports cards with the card voltage of 3.3 v only. do not set this bit to 1 unless the contents of the votselreg register are 0x01. 3, 2 reserved 0 is returned when read 1 reserved write 0 when write. 0 is returned when read. 0 reserved 0 is returned when read chapter 17 compactflash controller (ecu) user ? s manual u14272ej3v0um 337 17.4.4 itgenctreg (index: 0x03) bit 76543210 name ri_en crdrst crdtyp reserved irqsel3 irqsel2 irqsel1 irqsel0 r/w r/w r/w r/w r r/w r/w r/w r/w reset 00000011 bit name function 7 ri_en ring indicate enable. this bit is used to switch the function of the stschg#/ri# signal from the i/o card. the ring indicator function cannot be used in the v r 4181 so that 0 must be written to this bit. 0 : used as the stschg#. the current status of the signal is read from the if_stat_reg register if this signal is configures as a source for the card status change interrupt. 1 : used as the ri# for memory pc cards, this bit has no function. 6 crdrst card reset. this bit is for a software reset to the pc card to which the status of the cf_reset signal is set. 0 : active the cf_reset signal will be active until this bit is set to 1. 1 : inactive 5 crdtyp card type 0 : memory card 1 : i/o card 4 reserved 0 is returned when read 3 to 0 irqsel(3:0) interrupt request steering for the i/o card ireq (cf_busy#) signal 0000 : irq is not used 0001 : rfu 0010 : rfu 0011 : irq3 is used 0100 : irq4 is used 0101 : irq5 is used 0110 : rfu 0111 : irq7 is used 1000 : rfu 1001 : irq9 is used 1010 : irq10 is used 1011 : irq11 is used 1100 : irq12 is used 1101 : rfu 1110 : irq14 is used 1111 : irq15 is used chapter 17 compactflash controller (ecu) user ? s manual u14272ej3v0um 338 17.4.5 cdstchgreg (index: 0x04) bit 76543210 name reserved reserved reserved reserved cd_chg rdy_chg reserved bat_dead r/w rrrrr/wr/wrr/w reset 00000000 bit name function 7 to 4 reserved 0 is returned when read 3 cd_chg card detect (cd1# and cd2# signals) status change 0 : not changed 1 : changed 2 rdy_chg ready (cf_busy# signal) change 0 : no change or i/o card installed 1 : a low-to-high change has been detected indicating that the memory card is ready to accept a new data transfer 1 reserved 0 is returned when read 0 bat_dead battery not usable or status change detection (cf_stschg# signal status) 0 : for memory cards, battery is good. for i/o cards, the ri_en bit of the itgenctreg register is set to 1, or the cf_stschg# signal is at high level. 1 : for memory cards, a battery dead condition has been detected. for i/o cards, the ri_en bit of the itgenctreg register is cleared to 0 and the cf_stschg# signal is at low level. when this bit is set to 1, the system software t hen has to read the status change register in the i/o card to determine the cause of stschg. caution compactflash cards do not support the bvd (battery status detection) signal so that the bvd2/spkr signal of the ecu is internally fixed to low level. this register indicates the source of the card status change interrupt request. each source can be enabled to generate this interrupt request by setting the corresponding bit in the crdstatreg register. the bits in this register become 0 if their corresponding enable bits are cleared to 0. if the exwrbk bit is set to 1 in the gloctrlreg register, sources for the card status change interrupt request is acknowledged when 1 is set to the cd_chg bit in the cdstchgreg register though it has been already set to 1. once acknowledged, the cd_chg bit is cleared to 0. the interrupt request signal caused by the card status change, if any of the irq lines is enabled, remains active until all the bits in this register become 0. if the exwrbk bit is not set to 1, the card status change interrupt request, when any of the irq lines are enabled, remains active until this register is read. in this mode, reading this register resets all status bits to 0, which has been set to 1. chapter 17 compactflash controller (ecu) user ? s manual u14272ej3v0um 339 17.4.6 crdstatreg (index: 0x05) bit 76543210 name sirqs3 sirqs2 sirqs1 sirqs0 cd_en rdy_en reserved bdead_en r/w r/w r/w r/w r/w r/w r/w r r/w reset 00000000 bit name function 7 to 4 sirqs(3:0) interrupt request steering for the i/o card stschg# (cf_busy#) signal. 0000 : irq is not used 0001 : rfu 0010 : rfu 0011 : irq3 is used 0100 : irq4 is used 0101 : irq5 is used 0110 : rfu 0111 : irq7 is used 1000 : rfu 1001 : irq9 is used 1010 : irq10 is used 1011 : irq11 is used 1100 : irq12 is used 1101 : rfu 1110 : irq14 is used 1111 : irq15 is used 3 cd_en card detect enable. enables a card status change interrupt request when a change has been detected on the cd1# or cd2# signals. 0 : disable 1 : enable 2 rdy_en ready enable. enables a card status change interrupt request when a transition has been detected on the cf_busy# signal. 0 : disable 1 : enable 1 reserved 0 is returned when read 0 bdead_en battery not usable or status change interrupt request enable. enables a card status change interrupt request when a change has been detected on the cf_stschg# signal (battery unusable status for memory cards or status change detection for i/o cards). 0 : disable 1 : enable for i/o cards, the ri_en bit of the itgenctreg register must be cleared to 0 in advance when using the interrupt request via the cf_stschg# signal. chapter 17 compactflash controller (ecu) user ? s manual u14272ej3v0um 340 17.4.7 adwinenreg (index: 0x06) bit 76543210 name iowen1 iowen0 reserved mwen4 mwen3 mwen2 mwen1 mwen0 r/w r/w r/w r r/w r/w r/w r/w r/w reset 00000000 bit name function 7, 6 iowen(1:0) i/o window enables. generates the card enable signals to the card when an i/o access occurs within the corresponding i/o address window. 0 : does not generate 1 : generates i/o addresses are output from the system bus directly to the card. caution the start and stop address register pairs must be set to values for the window to be used before setting these bits to 1. 5 reserved 0 is returned when read 4 to 0 mwen(4:0) memory window enables. generates the card enable signals to the card when a memory access occurs within the corresponding memory address window. 0 : does not generate 1 : generates when the system address is within the window, the computed address is output to the card. caution the start, stop, and offset address register pairs must be set to values for the window to be used before setting these bits to 1. remark a single bit corresponds to each window. chapter 17 compactflash controller (ecu) user ? s manual u14272ej3v0um 341 17.4.8 ioctrl_reg (index: 0x07) bit 76543210 name io1wt w1_iows io1_cs16 md io1dsz io0wt w0_iows io0_cs16 md io0dsz r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 io1wt i/o window 1 wait addition in 16-bit accesses 0 : no additional wait state 1 : adds 1 wait state 6 w1_iows i/o window 1 wait addition in 8-bit accesses 0 : no additional wait state 1 : adds 1 wait state 5 io1_cs16md i/o window 1 iocs16 source 0 : value of the io1dsz bit 1 : cf_iois16# signal from the card 4 io1dsz i/o window 1 access data size 0 : 8 bits 1 : 16 bits this bit has no function when the io1_cs16md bit is set to 1. 3 io0wt i/o window 0 wait addition in 16-bit accesses 0 : without additional wait state 1 : adds 1 wait state 2 w0_iows i/o window 0 wait addition in 8-bit accesses 0 : no additional wait state 1 : adds 1 wait state 1 io0_cs16md i/o window 0 iocs16 source 0 : value of the io0dsz bit 1 : cf_iois16# signal from the card 0 io0dsz i/o window 0 access data size 0 : 8 bits 1 : 16 bits this bit has no function when the io0_cs16md bit is set to 1. chapter 17 compactflash controller (ecu) user ? s manual u14272ej3v0um 342 17.4.9 ioadslbnreg (index: 0x08, 0x0c) remark n = 0, 1 ioadslb0reg (0x08): for window 0 ioadslb1reg (0x0c): for window 1 bit 76543210 name starta7 starta6 starta5 starta4 starta3 starta2 starta1 starta0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 to 0 starta(7:0) i/o window start address bits 7 to 0 low-order address bits used to determine the start address of an i/o address window. minimum 1 byte can be specified for the i/o address window. 17.4.10 ioadshbnreg (index: 0x09, 0x0d) remark n = 0, 1 ioadshb0reg (0x09): for window 0 ioadshb1reg (0x0d): for window 1 bit 76543210 name starta15 starta14 starta13 starta12 starta11 starta10 starta9 starta8 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 to 0 starta(15:8) i/o window start address bits 15 to 8 high-order address bits used to determine the start address of an i/o address window. remark address bits 25 to 16 of an i/o window address are fixed to 0. therefore, an i/o window is always mapped to the address space between 0x1400 0000 and 0x1400 ffff, which is the first 64 kb of the isa-io space. chapter 17 compactflash controller (ecu) user ? s manual u14272ej3v0um 343 17.4.11 ioslbnreg (index: 0x0a, 0x0e) remark n = 0, 1 ioslb0reg (0x0a): for window 0 ioslb1reg (0x0e): for window 1 bit 76543210 name stopa7 stopa6 stopa5 stopa4 stopa3 stopa2 stopa1 stopa0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 to 0 stopa(7:0) i/o window stop address bits 7 to 0 low-order address bits used to determine the stop address of an i/o address window. 17.4.12 ioshbnreg (index: 0x0b, 0x0f) remark n = 0, 1 ioshb0reg (0x0b): for window 0 ioshb1reg (0x0f): for window 1 bit 76543210 name stopa15 stopa14 stopa13 stopa12 stopa11 stopa10 stopa9 stopa8 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 to 0 stopa(15:8) i/o window stop address bits 15 to 8 high-order address bits used to determine the stop address of an i/o address window. remark address bits 25 to 16 of an i/o window address are fixed to 0. therefore, an i/o window is always mapped to the address space between 0x1400 0000 and 0x1400 ffff, which is the first 64 kb of the isa-io space. chapter 17 compactflash controller (ecu) user ? s manual u14272ej3v0um 344 17.4.13 sysmemslnreg (index: 0x10, 0x18, 0x20, 0x28, 0x30) remark n = 0 to 4 sysmemsl0reg (0x10): for window 0 sysmemsl3reg (0x28): for window 3 sysmemsl1reg (0x18): for window 1 sysmemsl4reg (0x30): for window 4 sysmemsl2reg (0x20): for window 2 bit 76543210 name mwstart a19 mwstart a18 mwstart a17 mwstart a16 mwstart a15 mwstart a14 mwstart a13 mwstart a12 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 to 0 mwstarta(19:12) memory window start address bits 19 to 12 low-order address bits used to determine the start address of a memory address window. minimum 4 kb can be specified for memory address window. 17.4.14 memwidn_reg (index: 0x11, 0x19, 0x21, 0x29, 0x31) remark n = 0 to 4 memwid0_reg (0x11): for window 0 memwid3_reg (0x29): for window 3 memwid1_reg (0x19): for window 1 memwid4_reg (0x31): for window 4 memwid2_reg (0x21): for window 2 bit 76543210 name dwidth zwsen mwstart a25 mwstart a24 mwstart a23 mwstart a22 mwstart a21 mwstart a20 r/w r/w r/w r/w r\w r/w r/w r/w r/w reset 00000000 bit name function 7 dwidth memory window data width 0 : 8 bits 1 : 16 bits 6 zwsen zero wait state enable. this bit is used to set whether the zero wait state is requested to the isa bridge in memory accesses. 0 : does not request 1 : requests 5 to 0 mwstarta(25:20) memory window start address bits 25 to 20 this register is used to set the memory window data width, zero wait state enable, and high-order address bits used to determine the start address of a memory address window. chapter 17 compactflash controller (ecu) user ? s manual u14272ej3v0um 345 17.4.15 sysmemelnreg (index: 0x12, 0x1a, 0x22, 0x2a, 0x32) remark n = 0 to 4 sysmemel0reg (0x12): for window 0 sysmemel3reg (0x2a): for window 3 sysmemel1reg (0x1a): for window 1 sysmemel4reg (0x32): for window 4 sysmemel2reg (0x22): for window 2 bit 76543210 name mwstopa 19 mwstopa 18 mwstopa 17 mwstopa 16 mwstopa 15 mwstopa 14 mwstopa 13 mwstopa 12 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 to 0 mwstopa(19:12) memory window stop address bits 19 to 12 low-order address bits used to determine the stop address of a memory address window. 17.4.16 memseln_reg (index: 0x13, 0x1b, 0x23, 0x2b, 0x33) remark n = 0 to 4 memsel0_reg (0x13): for window 0 memsel3_reg (0x2b): for window 3 memsel1_reg (0x1b): for window 1 memsel4_reg (0x33): for window 4 memsel2_reg (0x23): for window 2 bit 76543210 name m16w1 m16w0 mwstopa 25 mwstopa 24 mwstopa 23 mwstopa 22 mwstopa 21 mwstopa 20 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7, 6 m16w(1:0) memory window wait state select for 16-bit accesses 00 : no additional wait state 01 : 2 additional wait states 10 : 3 additional wait states 11 : 4 additional wait states 5 to 0 mwstopa(25:20) memory window stop address bits 25 to 20 the ecu automatically inserts wait states when memory windows are accessed in 16-bit width. chapter 17 compactflash controller (ecu) user ? s manual u14272ej3v0um 346 17.4.17 memofflnreg (index: 0x14, 0x1c, 0x24, 0x2c, 0x34) remark n = 0 to 4 memoffl0reg (0x14): for window 0 memoffl3reg (0x2c): for window 3 memoffl1reg (0x1c): for window 1 memoffl4reg (0x34): for window 4 memoffl2reg (0x24): for window 2 bit 76543210 name offseta 19 offseta 18 offseta 17 offseta 16 offseta 15 offseta 14 offseta 13 offseta 12 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 to 0 offseta(19:12) card memory offset address bits 19 to 12 this register is defined to maintain compatibility with the exca. settings in this register have no meaning in the v r 4181. 17.4.18 memoffhnreg (index: 0x15, 0x1d, 0x25, 0x2d, 0x35) remark n = 0 to 4 memoffh0reg (0x15): for window 0 memoffh3reg (0x2d): for window 3 memoffh1reg (0x1d): for window 1 memoffh4reg (0x35): for window 4 memoffh2reg (0x25): for window 2 bit 76543210 name wp reg offseta 25 offseta 24 offseta 23 offseta 22 offseta 21 offseta 20 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 wp write protect to the card through a memory window 0 : write operation allowed 1 : write operation prohibited 6 reg reg# (cf_reg#) signal active of the compactflash. this bit is used to set which memory is to be used on accesses to the compactflash card. 0 : common memory 1 : attribute memory 5 to 0 offseta(25:20) card memory offset address bits 25 to 20. remark this is defined to maintain compatibility with the exca. settings in these bits have no meaning in the v r 4181. chapter 17 compactflash controller (ecu) user ? s manual u14272ej3v0um 347 17.4.19 dtgenclreg (index: 0x16) bit 76543210 name reserved reserved swcdint cdrsmen reserved reserved cfgrsten dly16inh r/w r r w r/w r r r/w r/w reset 00000000 bit name function 7, 6 reserved 0 is returned when read 5 swcdint software card detect interrupt request 1 : generates interrupt request this bit is valid when the cd_en bit is set to 1 in the crdstatreg register. 0 is returned when read. 4 cdrsmen card detect resume enable 1 : enables notification of change on cd1# and cd2# inputs this bit is valid when the cd_en bit is set to 1 in the crdstatreg register. 0 is returned when read. 3, 2 reserved 0 is returned when read 1 cfgrsten configuration reset enable 1 : enables initializing registers on high level of both cd1# and cd2# inputs the registers involved are all i/o registers, all memory registers, itgenctreg register, and adwinenreg register. 0 dly16inh 16-bit memory delay prohibit. this bit is used to set whether the falling edge of the we# and oe# (cf_we# and cf_oe#) signals of the compactflash is delayed in synchronization with sysclk when a memory window is set to be 16 bit in the dwidth bit of the memwidn_reg register. 0 : delayed 1 : not delayed the functionality and acknowledgment of this software interrupt request operate in the same way as those of the hardware-generated interrupt requests. the functionality and acknowledgement of the hardware card detect or card status change interrupt request are not affected by the setting of the swcdint bit. if card detect or card status change is signaled through the cd1# and cd2# inputs, a hardware card detect or card status change interrupt request is generated. when the cdrsmen bit is set to 1, the rio# signal (internal) goes from high level to low and the cd_chg bit in the cdstchgreg register is set to 1. the rio# signal remains low until either a read or a write of 1 to the cd_chg bit (acknowledge cycle), which causes the cd_chg bit to be reset to 0 and the rio# signal to go from low level to high. if the card status change is routed to any of the irq signals, the setting of this bit to 1 prevents the irq signal from going active as a result of a hardware card detect status change. once the software detects a card detect status change interrupt request from the rio# signal by reading the cdstchgreg register, it must issue a software card detect change interrupt request so that the card detect change condition generates an active interrupt request on the irq signal. chapter 17 compactflash controller (ecu) user ? s manual u14272ej3v0um 348 17.4.20 gloctrlreg (index: 0x1e) bit 76543210 name reserved reserved reserved reserved reserved exwrbk reserved reserved r/w rrrrrr/wrr reset 00000000 bit name function 7 to 3 reserved 0 is returned when read 2 exwrbk card status change interrupt request acknowledgement. 0 : reading of the cdstchgreg register each bit of the register is cleared after read. 1 : writing 1 to the cdstchgreg register each bit of the register is cleared after write of 1. 1, 0 reserved 0 is returned when read 17.4.21 voltsenreg (index: 0x1f) bit 76543210 name reserved reserved reserved reserved reserved reserved vs2 vs1 r/w rrrrrrrr reset 00000010 bit name function 7 to 2 reserved 0 is returned when read 1, 0 vs(2:1) voltage sense status these bits are read-only and hardwired to 10 binary since the v r 4181 has no voltage sense pins. chapter 17 compactflash controller (ecu) user ? s manual u14272ej3v0um 349 17.4.22 voltselreg (index: 0x2f) bit 76543210 name reserved reserved reserved reserved reserved reserved vccen1 vccen0 r/w rrrrrrr/wr/w reset 00000010 bit name function 7 to 2 reserved 0 is returned when read 1, 0 vccen(1:0) card connection status 01 : 3.3 v card connected 10 : no card connected caution do not perform any write to this bit. if the pwren bit of the pwrrsetdrv register is set to 1 when the vccen(1:0) bits are 01, the cf_vccen# signal becomes active. remark the v r 4181 supports cards with the card voltage of 3.3 v only. chapter 17 compactflash controller (ecu) user ? s manual u14272ej3v0um 350 17.5 memory mapping of compactflash card (1) memory window in the v r 4181, memory windows can be placed at any address in the isa memory space. the start address of a memory window is output without modification to the v r 4181 ? s add pins. however, spaces used for programmable chip select, lcd chip select, etc. must not be specified as a memory window. the compactflash memory space is 2 kb and the minimum memory window size is 4 kb. accordingly, when using compactflash with the v r 4181, the card ? s entire memory space is mapped to a single memory window. mapping starts from the lsb. the remaining part of the memory window becomes a mirror area occupying the lower 2 kb. figure 17-2. mapping of compactflash memory space 0x13ff ffff 0x1ppp p000 0x1qqq q000 0x0000 0000 0x1sss s000 0x1rrr r000 v r 4181 isa memory space (internal) (64 mb) memory window m memory window n 0x3f ffff 0x00 0000 v r 4181 space specified via add pins (4 mb) memory window m memory window n 0x7ff 0x000 compactflash card common memory space attribute memory space (2 kb) remark m, n = 0 to 4 p, q, r, s = don ? t care chapter 17 compactflash controller (ecu) user ? s manual u14272ej3v0um 351 (2) i/o window in the v r 4181, the i/o window can be mapped to any address within the external isa i/o space ? s lower 64 kb. the start address of a window is output without modification to the v r 4181 ? s add pins. when using the compactflash card, do not map a space for programmable chip select or another external device to the lower 64 kb within external isa i/o space where i/o windows are assigned. figure 17-3. mapping of compactflash i/o space 0x17ff ffff 0x1400 0000 v r 4181 isa i/o space (internal) (64 mb) i/o window m i/o window n 0x3f ffff 0x00 0000 v r 4181 space specified via add pins (4 mb) 0x7ff 0x000 compactflash card i/o space (2 kb) 0x1401 0000 i/o window m i/o window n 0x01 0000 i/o window m i/o window n remark m, n = 0 or 1 chapter 17 compactflash controller (ecu) user ? s manual u14272ej3v0um 352 17.6 controlling bus when compactflash card is used access to the compactflash card is made via the isa bridge. the address, data, and command signals operate based on external isa cycles. the operations of the signals that control the bus size and wait state (memcs16#, iocs16#, and iordy) can be set in the ecu. 17.6.1 controlling bus size when the memory window is accessed, the data bus width is set in the dwidth bit of the memwidn_reg register (n = 0 to 4). this setting is output from the ecu to the isa bridge as the source of the memcs16# signal. when the i/o window is accessed, the source of the data width is selected from the cf_iois16# signal or iondsz bit (n = 0 or 1) via the ion_cs16md bit (n = 0 or 1) of the ioctrl_reg register. if the cf_iois16# signal is selected, its status is output from the ecu to the isa bridge as the source of the iocs16# signal. if the iondsz bit is selected, the inverted setting of the iondsz bit is output. 17.6.2 controlling wait the number of wait states of the external isa cycle can be selected from four types by using the memws(1:0) and iows(1:0) bits of the xisactl register of the isa bridge, regardless of whether the memory or i/o is accessed. in addition, the ecu deasserts the iordy signal and extends the bus cycle if the cf_wait# signal from the compactflash card is asserted. additional wait states can be controlled by ecu settings. (1) wait when memory window is accessed the zero wait state can be enabled or disabled via the zwsen bit of the memwidn_reg register (n = 0 to 4). (a) if zero wait state is enabled a wait state is not added regardless of the bus size. therefore, wait states are inserted only during the period set in the memws(1:0) bits of the xisactl register. (b) if zero wait state is disabled the number of wait states selected in the m16w(1:0) bits of the memseln_reg register (n = 0 to 4) is added in the 16-bit access mode. in the 8-bit access mode, a 4 sysclk-cycle wait is added. (2) wait when i/o window is accessed (a) 16-bit access a 2 sysclk-cycle wait is added if the ionwt bit of the ioctrl_reg register (n = 0 or 1) is set to 1. a 1 sysclk-cycle wait is added if the ionwt bit of the ioctrl_reg register (n = 0 or 1) is cleared to 0. (b) 8-bit access a 4 sysclk-cycle wait is added if the wn_iows bit of the ioctrl_reg register (n = 0 or 1) is set to 1. a 3 sysclk-cycle wait is added if the wn_iows bit of the ioctrl_reg register (n = 0 or 1) is cleared to 0. user?s manual u14272ej3v0um 353 chapter 18 led control unit (led) 18.1 general this unit switches on and off of leds at a regular interval. the interval can be set via software. 18.2 register set the led registers are listed below. table 18-1. led registers physical address r/w register symbol function 0x0b00 0240 r/w ledhtsreg led on time set register 0x0b00 0242 r/w ledltsreg led off time set register 0x0b00 0248 r/w ledcntreg led control register 0x0b00 024a r/w ledastcreg led auto stop time setting register 0x0b00 024c r/w ledintreg led interrupt register these registers are described in detail below. chapter 18 led control unit (led) user?s manual u14272ej3v0um 354 18.2.1 ledhtsreg (0x0b00 0240) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst00000000 other resets00000000 bit 76543210 name reserved reserved reserved hts4 hts3 hts2 hts1 hts0 r/w r r r r/w r/w r/w r/w r/w rtcrst00010000 other resets 0 0 0 note note note note note bit name function 15 to 5 reserved 0 is returned when read 4 to 0 hts(4:0) led on time setting 11111 : 1.9375 seconds : 10000 : 1 second : 01000 : 0.5 seconds : 00100 : 0.25 seconds : 00010 : 0.125 seconds 00001 : 0.0625 seconds 00000 : prohibited note a value before reset is retained. this register is used to set the led?s on time (high level width of ledout). the on time ranges from 0.0625 to 1.9375 seconds and can be set in 0.0625 second units. the initial setting is 1 second. this register must not be changed once the ledenable bit of the ledcntreg register has been set to 1. the operation is not guaranteed if a change is made after that point. chapter 18 led control unit (led) user?s manual u14272ej3v0um 355 18.2.2 ledltsreg (0x0b00 0242) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst 00000000 other resets 00000000 bit 76543210 name reserved lts6 lts5 lts4 lts3 lts2 lts1 lts0 r/w r r/w r/w r/w r/w r/w r/w r/w rtcrst 00100000 other resets 0 note note note note note note note bit name function 15 to 7 reserved 0 is returned when read 6 to 0 lts(6:0) led off time setting 1111111 : 7.9375 seconds : 1000000 : 4 seconds : 0100000 : 2 seconds : 0010000 : 1 second : 0001000 : 0.5 seconds : 0000100 : 0.25 seconds : 0000010 : 0.125 seconds 0000001 : 0.0625 seconds 0000000 : prohibited note a value before reset is retained. this register is used to set the led?s off time (low level width of ledout). the off time ranges from 0.0625 to 7.9375 seconds and can be set in 0.0625 second units. the initial setting is 2 seconds. this register must not be changed once the ledenable bit of ledcntreg register has been set to 1. the operation is not guaranteed if a change is made after that point. chapter 18 led control unit (led) user?s manual u14272ej3v0um 356 18.2.3 ledcntreg (0x0b00 0248) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst00000000 other resets00000000 bit 76543210 name reserved reserved reserved reserved reserved ledhlb ledstop ledenable r/w r r r r r r r/w r/w rtcrst00000010 other resets000000 note note bit name function 15 to 3 reserved 0 is returned when read 2 ledhlb led status indication 1 : on 0 : off 1 ledstop led blink auto stop setting 1 : automatically stops 0 : does not stop automatically 0 ledenable led blink setting 1 : blinks 0 : does not blink note a value before reset is retained. this register is used to make various led settings. caution when setting led to blink, make sure that a value other than zero has already been set to the ledhtsreg, ledltsreg, and ledastcreg registers. the operation is not guaranteed if zero is set to these registers. chapter 18 led control unit (led) user?s manual u14272ej3v0um 357 18.2.4 ledastcreg (0x0b00 024a) bit 151413121110 9 8 name astc15 astc14 astc13 astc12 astc11 astc10 astc9 astc8 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00000100 other resets00000100 bit 76543210 name astc7 astc6 astc5 astc4 astc3 astc2 astc1 astc0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst10110000 other resets10110000 bit name function 15 to 0 astc(15:0) led auto stop time count this register is used to set the number of on/off times prior to automatic stopping of led blink. the set value is read on a read. the initial setting is 1,200 times of on/off pairs (i.e. one hour in which each time includes one second of on time and two seconds of off time). the pair of operations in which the led is switched on once and off once is counted as ?1? by this counter. the counter counts down from the set value and an ledint interrupt request occurs when it reaches zero. caution setting a zero to this register is prohibited. the operation is not guaranteed if zero is set to this register. chapter 18 led control unit (led) user?s manual u14272ej3v0um 358 18.2.5 ledintreg (0x0b00 024c) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr rtcrst00000000 other resets00000000 bit 76543210 name reserved reserved reserved reserved reserved reserved reserved ledint r/w rrrrrrrr/w rtcrst00000000 other resets00000000 bit name function 15 to 1 reserved 0 is returned when read 0 ledint auto stop interrupt request. cleared to 0 when 1 is written. 1 : occurred 0 : not occurred this register indicates when an auto stop interrupt request has occurred. an auto stop interrupt request occurs when 1 has already been set to both the ledstop bit and the ledenable bit of the ledcntreg register if ledastcreg register is cleared to 0. when this interrupt occurs, the ledstop bit and the ledenable bit of the ledcntreg register are both cleared to 0. chapter 18 led control unit (led) user?s manual u14272ej3v0um 359 18.3 operation flow set ledhtsreg set ledltsreg ledcntreg ledstop = 1 set ledastcreg ledcntreg ledenable = 1 led blinking time setting ledhtsreg set led on time. ledltsreg set led off time. ledastcreg set number of leds blinking. led auto stop setting ledstop set this bit to enable the led blink auto stop function. this setting terminates led blinking automatically after blinking time set above has elapaed. led blinking operation start ledenable set this bit to start led blinking operation. caution setting these registers to 0 is prohibited because it may cause undefined operation. led blinking operation supervising the auto stop counter led blinking terminates when the auto stop counter reaches 0. led blinking operation termination ledenable led blinking operation is terminated by setting 0 to this bit. led blinking operation terminate interrupt request generation ledint an interrupt request to the icu is generated when 1 is set to this bit. caution setting the ledenable and ledstop bits to 0 is prohibited because it may cause undefined operation. yes no ledenable = 0 ledstop = 0 ledint = 1 register initial setting ledhtsreg: 0x0010 (led on time available) ledltsreg: 0x0020 (led off time available) ledcntreg: 0x0002 ledastcreg: 0x04b0 leds blinking operation start condition leds blink register initial setting note auto stop counter = 0 leds off software end start hardware note initial setting for each register must be performed when a power is supplied to device for the first time, regardless whether leds blinking function is used or not. user?s manual u14272e3v0um 360 chapter 19 serial interface unit 1 (siu1) 19.1 general the siu1 is a serial interface that conforms to the rs-232-c communication standard and is equipped with two one-channel interfaces, one for transmission and one for reception. this unit is functionally compatible with the ns16550 except for the additional clock control logic to permit the 16650 core clock source to be stopped. figure 19-1. siu1 block diagram v r 4181 uart1 rxd1 txd1 rts1# activity timer 1 dtr1# dcd1# clk32k seclk_siu uart1_clock siu1 caution no clock is supplied to the siu1 in the initial state. when using the siu1, set the msksiu18m bit of the cmuclkmsk register in the mba host bridge to 1 in advance so that the clock is supplied. 19.2 clock control logic the power of the 16550 core can be managed by monitoring activity on the modem status pins and writes to the transmit buffer. the clock control logic for the 16550 core monitors activity on the four serial interface input signals; rxd1, rts1#, dcd1#, and dtr1#. it also monitors writes to the 16550 transmit buffer. each source has an associated mask bit which prevents a source from causing reset of the activity timer. activity on the rxd1, rts1#, dcd1#, and dtr1# inputs is defined as any change of state (high to low or low to high). when no unmasked activity has been detected on any of the inputs, and no writes have occurred to the transmit buffer within the programmed time-out period specified in the activity timer block, the uart1_clock is stopped. the uart1_clock will remain stopped until any activity is detected on the monitored sources. chapter 19 serial interface unit 1 (siu1) user ? s manual u14272ej3v0um 361 19.3 register set the siu1 registers are listed below. table 19-1. siu1 registers physical address lcr7 r/w register symbol function 0x0c00 0010 0 r siurb_1 receive buffer register (read) w siuth_1 transmit holding register (write) 1 r/w siudll_1 divisor latch (least significant byte) register 0x0c00 0011 0 r/w siuie_1 interrupt enable register 1 r/w siudlm_1 divisor latch (most significant byte) register 0x0c00 0012 ? r siuiid_1 interrupt identification register (read) ? w siufc_1 fifo control register (write) 0x0c00 0013 ? r/w siulc_1 line control register 0x0c00 0014 ? r/w siumc_1 modem control register 0x0c00 0015 ? r siuls_1 line status register 0x0c00 0016 ? r/w siums_1 modem status register 0x0c00 0017 ? r/w siusc_1 scratch register 0x0c00 0019 ? r/w siureset_1 siu reset register 0x0c00 001c ? r/w siuactmsk_1 siu activity mask register 0x0c00 001e ? r/w siuadttmr_1 siu activity timer register remark lcr7 is bit 7 of the siulc_1 register. chapter 19 serial interface unit 1 (siu1) user ? s manual u14272ej3v0um 362 19.3.1 siurb_1 (0x0c00 0010: lcr7 = 0, read) bit 76543210 name rxd7 rxd6 rxd5 rxd4 rxd3 rxd2 rxd1 rxd0 r/w rrrrrrrr rtcrst undefined undefined undefined undefined undefined undefined undefined undefined other resets undefined undefined undefined undefined undefined undefined undefined undefined bit name function 7 to 0 rxd(7:0) serial receive data this register stores receive data used in serial communications. to access this register, set the lcr7 bit (bit 7 of the siulc_1 register) to 0. 19.3.2 siuth_1 (0x0c00 0010: lcr7 = 0, write) bit 76543210 name txd7 txd6 txd5 txd4 txd3 txd2 txd1 txd0 r/w wwwwwwww rtcrst undefined undefined undefined undefined undefined undefined undefined undefined other resets undefined undefined undefined undefined undefined undefined undefined undefined bit name function 7 to 0 txd(7:0) serial transmit data this register stores transmit data used in serial communications. to access this register, set the lcr7 bit (bit 7 of the siulc_1 register) to 0. 19.3.3 siudll_1 (0x0c00 0010: lcr7 = 1) bit 76543210 name dll7 dll6 dll5 dll4 dll3 dll2 dll1 dll0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst undefined undefined undefined undefined undefined undefined undefined undefined other resets undefined undefined undefined undefined undefined undefined undefined undefined bit name function 7 to 0 dll(7:0) baud rate divisor (low-order byte) this register is used to set the divisor (division rate) for the baud rate generator. the data in this register and the data in the siudlm_1 register as upper 8 bits are together handled as 16-bit data. to access this register, set the lcr7 bit (bit 7 of the siulc_1 register) to 1. chapter 19 serial interface unit 1 (siu1) user ? s manual u14272ej3v0um 363 19.3.4 siuie_1 (0x0c00 0011: lcr7 = 0) bit 76543210 name reserved reserved reserved reserved ie3 ie2 ie1 ie0 r/w r r r r r/w r/w r/w r/w rtcrst00000000 other resets00000000 bit name function 7 to 4 reserved 0 is returned when read 3 ie3 modem status interrupt 1 : enable 0 : prohibit 2 ie2 receive status interrupt 1 : enable 0 : prohibit 1 ie1 transmit holding register empty interrupt 1 : enable 0 : prohibit 0 ie0 receive data ready interrupt or character timeout interrupt in fifo mode 1 : enable 0 : prohibit this register is used to specify interrupt enable/prohibit settings for the five types of interrupt requests used in the siu1. an interrupt is enabled by setting the corresponding bit to 1. overall use of interrupt functions can be halted by setting bits 0 to 3 of this register to 0. when interrupts are prohibited, ? pending ? is not displayed in the iir0 bit in the siuiid_1 register even when interrupt conditions have been met. other functions in the siu1 are not affected even though interrupts are prohibited and the settings in the siuls_1 register and siums_1 register are valid. to access this register, set the lcr7 bit (bit 7 of the siulc_1 register) to 0. chapter 19 serial interface unit 1 (siu1) user ? s manual u14272ej3v0um 364 19.3.5 siudlm_1 (0x0c00 0011: lcr7 = 1) bit 76543210 name dlm7 dlm6 dlm5 dlm4 dlm3 dlm2 dlm1 dlm0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst undefined undefined undefined undefined undefined undefined undefined undefined other resets undefined undefined undefined undefined undefined undefined undefined undefined bit name function 7 to 0 dlm(7:0) baud rate divisor (high-order byte) this register is used to set the divisor (division rate) for the baud rate generator. the data in this register and the data in the siudll_1 register as lower 8 bits are together handled as 16-bit data. to access this register, set the lcr7 bit (bit 7 of the siulc_1 register) to 1. the relationship between baud rates and the settings of the siudll_1 and siudlm_1 registers are as follows. chapter 19 serial interface unit 1 (siu1) user ? s manual u14272ej3v0um 365 table 19-2. correspondence between baud rates and divisors baud rate (bps) divisor (dlm(7:0)||dll(7:0)) 1-clock width ( s) 50 23040 20000.00 75 15360 13333.33 110 10473 9090.91 134.5 8565 7434.94 150 7680 6666.67 300 3840 3333.33 600 1920 1666.67 1200 960 833.33 1800 640 555.56 2000 576 500.00 2400 480 416.67 3600 320 277.78 4800 240 208.33 7200 160 138.89 9600 120 104.17 19200 60 52.08 38400 30 26.04 57600 20 17.36 115200 10 8.68 128000 9 7.81 144000 8 6.94 192000 6 5.21 230400 5 4.34 288000 4 3.47 384000 3 2.60 576000 2 1.74 1152000 1 0.868 chapter 19 serial interface unit 1 (siu1) user ? s manual u14272ej3v0um 366 19.3.6 siuiid_1 (0x0c00 0012: read) bit 76543210 name iir7 iir6 reserved reserved iir3 iir2 iir1 iir0 r/w rrrrrrrr rtcrst00000001 other resets00000001 bit name function 7, 6 iir(7:6) becomes 11 when fcr0 bit = 1 5, 4 reserved 0 is returned when read 3 iir3 pending of the character timeout interrupt request (in fifo mode) 1 : no pending 0 : pending 2, 1 iir(2:1) indicates the priority level of interrupts. see the following table. 0 iir0 pending interrupt requests 1 : no pending 0 : pending this register indicates priority levels for interrupts and existence of pending interrupt requests. from highest to lowest priority, the involved interrupts are the receive line status, the receive data ready, the character timeout, the transmit holding register empty, and the modem status. the content of the iir3 bit is valid only in the fifo mode and it is always 0 in the 16450 mode. the iir2 bit becomes 1 when the iir3 bit is set to 1. chapter 19 serial interface unit 1 (siu1) user ? s manual u14272ej3v0um 367 table 19-3. interrupt function siuiid_1 register interrupt set/reset function bit 3 note bit 2 bit 1 priority level interrupt type interrupt source interrupt reset control 0 1 1 highest (1st) receive line status overrun error, parity error, framing error, or break interrupt read line status register 0 1 0 2nd receive data ready receive data exists or has reached the trigger level. read the receive buffer register or lower the data in the fifo than trigger level. 1 1 0 2nd character timeout during the time period for the four most recent characters, not one character has been read from the receive fifo nor has a character been input to the receive fifo. during this period, at least one character has been held in the receive fifo. read receive buffer register 0 0 1 3rd transmit holding register empty transmit register is empty read iir (if it is the interrupt source) or write to transmit holding register 0 0 0 4th modem status cts1#, dsr1#, or dcd1# read modem status register note fifo mode only. chapter 19 serial interface unit 1 (siu1) user ? s manual u14272ej3v0um 368 19.3.7 siufc_1 (0x0c00 0012: write) bit 76543210 name fcr7 fcr6 reserved reserved fcr3 fcr2 fcr1 fcr0 r/w ww r r wwww rtcrst00000000 other resets00000000 bit name function 7, 6 fcr(7:6) receive fifo trigger level 11 : 14 bytes 10 : 8 bytes 01 : 4 bytes 00 : 0 bytes 5, 4 reserved 0 is returned when read 3 fcr3 switch between 16450 mode and fifo mode 1 : from 16450 mode to fifo mode 0 : from fifo mode to 16450 mode 2 fcr2 transmit fifo and its counter clear. cleared to 0 when 1 is written. 1 : fifo and its counter clear 0 : normal 1 fcr1 receive fifo and its counter clear. cleared to 0 when 1 is written. 1 : fifo and its counter clear 0 : normal 0 fcr0 receive/transmit fifo enable. cleared to 0 when 1 is written. 1 : enable 0 : disable this register is used to control the fifos. chapter 19 serial interface unit 1 (siu1) user ? s manual u14272ej3v0um 369 ? fifo interrupt modes when receive fifo is enabled and receive interrupt requests are enabled, receive interrupts can occur as described below. 1. when the fifo is reached to the specified trigger level, a receive data ready interrupt request is notified to the cpu. this interrupt is cleared when the fifo goes below the trigger level. 2. when the fifo is reached to the specified trigger level, the siuiid_1 register indicates a receive data ready interrupt request. same as the interrupt above, the suiid_1 register is cleared when the fifo goes below the trigger level. 3. the receive line status interrupt is assigned to a higher priority level than the receive data ready interrupt. 4. when characters are transferred from the shift register to the receive fifo, 1 is set to the lsr0 bit of the siuls_1 register. the value of this bit returns to 0 when the fifo becomes empty. when receive fifo is enabled and receive interrupts are enabled, receive fifo timeout interrupt requests can occur as described below. 1. followings are the conditions under which fifo timeout interrupt requests occur. at least one character is being stored in the fifo. the time required for sending four characters has elapsed since the serial reception of the last character (includes the time for the second stop bit in cases where it is specified that two stop bits are required). the time required for sending four characters has elapsed since the last read of the fifo by the cpu. the time between receiving the last character and issuing a timeout interrupt request is a maximum of 160 ms when operating at 300 baud and receiving 12-bit data. 2. the transfer time for a character is calculated based on the baud rate clock for reception (internal) (which is why the elapsed time is in proportion to the baud rate). 3. once a timeout interrupt request has occurred, the timeout interrupt is cleared and the timer is reset as soon as the cpu reads one character from the receive fifo. 4. if no timeout interrupt request has occurred, the timer is reset when a new character is received or when the cpu reads the receive fifo. chapter 19 serial interface unit 1 (siu1) user ? s manual u14272ej3v0um 370 when transmit fifo is enabled and transmit interrupts are enabled, transmit interrupt requests can occur as described below. 1. when the transmit fifo becomes empty, a transmit holding register empty interrupt request occurs. this interrupt request is cleared when a character is written to the transmit holding register (from one to 16 characters can be written to the transmit fifo during servicing of this interrupt), or when the siuiid_1 register is read. 2. if there are not at least two bytes of character data in the transmit fifo between one time when the lsr5 bit = 1 (transmit fifo is empty) in the siuls_1 register and the next time when the lsr5 bit = 1, transmit fifo empty status is reported to the iir bits after a delay period calculated as ? the time for one character ? the time for the last stop bit(s) ? . when transmit interrupts are enabled, the first transmit interrupt request that occurs after the fcr0 bit (fifo enable bit) in the siufc_1 register is overwritten is indicated immediately. the priority level of the character timeout interrupt and receive fifo trigger level interrupt is the same as that of the receive data ready interrupt. the priority level of the transmit fifo empty interrupt is the same as that of the transmit holding register empty interrupt. whether data to be transmitted exists or not in the transmit fifo and the transmit shift register, check the lsr6 bit of the siuls_1 register. the lsr5 bit of the siuls_1 register is used to check whether data to be transferred exists or not in the transmit fifo only. therefore, there may be data in the transmit shift register. fifo polling mode when the fcr0 bit = 1 (fifo is enabled) in the siufc_1 register, if the value of any or all of the siuie_1 register bits 3 to 0 becomes 0, siu1 enters fifo polling mode. because the transmit block and receive block are controlled separately, polling mode can be set for either or both blocks. when in this mode, the status of the transmit block and/or receive block can be checked by reading the siuls_1 register via a user program. when in the fifo polling mode, there is no notification when the trigger level is reached or when a timeout occurs, but the receive fifo and transmit fifo can still store characters as they normally do. chapter 19 serial interface unit 1 (siu1) user ? s manual u14272ej3v0um 371 19.3.8 siulc_1 (0x0c00 0013) bit 76543210 name lcr7 lcr6 lcr5 lcr4 lcr3 lcr2 lcr1 lcr0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00000000 other resets00000000 bit name function 7 lcr7 divisor latch access register switching 1 : divisor latch access register 0 : receive buffer, transmit holding register, interrupt enable register 6 lcr6 break control 1 : set break 0 : clear break 5 lcr5 parity fixing 1 : fixed parity 0 : parity not fixed 4 lcr4 parity setting 1 : even parity 0 : odd parity 3 lcr3 parity enable 1 : create parity (during transmission) or check parity (during reception) 0 : no parity (during transmission) or no checking (during reception) 2 lcr2 stop bit specification 1 : 1.5 bits (character length is 5 bits) 2 bits (character length is 6, 7, or 8 bits) 0 : 1 bit 1, 0 lcr(1:0) specifies the length of one character (number of bits) 11 : 8 bits 10 : 7 bits 01 : 6 bits 00 : 5 bits this register is used to specify the format for asynchronous data communication and exchange and to set the divisor latch access register. the lcr6 bit is used to send the break status to the receive side ? s uart. when the lcr6 bit = 1, the serial output (txd1) is forcibly set to the spacing (0) state. the setting of the lcr5 bit becomes valid according to settings in the lcr4 and lcr3 bits. chapter 19 serial interface unit 1 (siu1) user ? s manual u14272ej3v0um 372 19.3.9 siumc_1 (0x0c00 0014) bit 76543210 name reserved reserved reserved mcr4 mcr3 mcr2 mcr1 mcr0 r/w r r r r/w r/w r/w r/w r/w rtcrst00000000 other resets00000000 bit name function 7 to 5 reserved 0 is returned when read 4 mcr4 use of diagnostic testing (local loopback) 1 : enable 0 : disable 3 mcr3 out2 signal (internal) setting 1 : low level 0 : high level 2 mcr2 out1 signal (internal) setting 1 : low level 0 : high level 1 mcr1 rts1# output control 1 : low level 0 : high level 0 mcr0 dtr1# output control 1 : low level 0 : high level this register is used to control the interface with a modem or data set (or a peripheral device that emulates a modem). the settings of the mcr3 and mcr2 bits become valid only when the mcr4 bit is set to 1 (enable use of local loopback). local loopback the local loopback can be used to test the transmit/receive data path in siu1. the following operation (local loopback) is executed inside the siu1 when the mcr4 bit = 1. the transmit block ? s serial output (txd1) enters the marking state (1) and the serial input (rxd1) to the receive block is cut off. the transmit shift register ? s output is looped back to the receive shift register ? s input. the four modem control inputs (dsr1#, cts1#, ri (internal), and dcd1#) are cut off and the four modem control outputs (dtr1#, rts1#, out1 (internal), and out2 (internal)) are internally connected to the corresponding modem control inputs. the modem control output pins are forcibly set as inactive (high level). during this kind of loopback mode, transmitted data can be immediately and directly received. when in loopback mode, both transmit and receive interrupts can be used. the interrupt sources are external sources in relation to the transmit and receive blocks. although modem control interrupts can be used, the low- order four bits of the modem control register can be used instead of the four modem control inputs as interrupt sources. as usual, each interrupt is controlled by an interrupt enable register. chapter 19 serial interface unit 1 (siu1) user ? s manual u14272ej3v0um 373 19.3.10 siuls_1 (0x0c00 0015) bit 76543210 name lsr7 lsr6 lsr5 lsr4 lsr3 lsr2 lsr1 lsr0 r/w rrrrrrrr rtcrst01100000 other resets01100000 bit name function 7 lsr7 error detection (fifo mode) 1 : parity error, framing error, or break is detected. 0 : no error 6 lsr6 transmit block empty 1 : no data in transmit holding register and transmit shift register no data in transmit fifo (during fifo mode) 0 : data exists in transmit holding register or transmit shift register data exists in transmit fifo (during fifo mode) 5 lsr5 transmit holding register empty 1 : character is transferred to transmit shift register (during 16450 mode) transmit fifo is empty (during fifo mode) 0 : character is stored in transmit holding register (during 16450 mode) transmit data exists in transmit fifo (during fifo mode) 4 lsr4 break interrupt 1 : detected 0 : no break 3 lsr3 framing error 1 : detected 0 : no error 2 lsr2 parity error 1 : detected 0 : no error 1 lsr1 overrun error 1 : detected (receive data is overwritten) 0 : no error 0 lsr0 receive data ready 1 : receive data exists in fifo 0 : no receive data in fifo the cpu uses this register to get information related to data transfers. when lsr7 and lsr(4:1) bits are 1, reading this register clears these bits to 0. caution the lsr0 bit (receive data ready bit) is set before the serial data reception is completed. therefore, the lsr0 bit may not be cleared if the serial receive data is read from the siurb_1 register immediately after this bit is set. when reading data from the siurb_1 register, wait for the stop bit width time since the lsr0 bit is set. chapter 19 serial interface unit 1 (siu1) user ? s manual u14272ej3v0um 374 lsr7 bit is valid only in fifo mode, and it indicates always 0 in 16450 mode. the value of lsr4 bit becomes 1 when the spacing status (0) of receive data input is held longer than the time required for transmission of one word (start bit + data bits + parity bit + stop bit). when in fifo mode, if a break is detected for one character in the fifo, the character is regarded as an error character and the cpu is notified of a break when that character reaches the highest position in the fifo. when a break occurs, one ? zero ? character is sent to the fifo. when the rxd1 enters marking status, and the next valid start bit is received, the next character can be transmitted. the value of lsr3 bit becomes 1 when a zero (spacing level) stop bit is detected following the final data bit or parity bit. when in fifo mode, if a framing error is detected for one character in the fifo, the character is regarded as an error character and the cpu is notified of a framing error when that character reaches the highest position in the fifo. when a framing error occurs, the siu1 prepares for synchronization again. the next start bit is assumed to be the cause of the framing error and the next data is not accepted until the next start bit has been sampled twice. the value of lsr2 bit becomes 1 when a received character does not satisfy the even or odd parity specified in the lcr4 bit. when in fifo mode, if a parity error is detected for one character within the fifo, the character is regarded as an error character and the cpu is notified of a parity error when that character reaches the highest position in the fifo. the value of lsr1 bit becomes 1 when a character is transferred to the receive buffer register before reading by the cpu and the previous character is lost. when in fifo mode, if the data continues to be transferred to the fifo though it exceeds the trigger level, even after the fifo becomes full an overrun error will not occur until all characters are stored in the shift register. the cpu is notified as soon as an overrun error occurs. the characters in the shift register are overwritten and are not transferred to the fifo. chapter 19 serial interface unit 1 (siu1) user ? s manual u14272ej3v0um 375 19.3.11 siums_1 (0x0c00 0016) bit 76543210 name msr7 msr6 msr5 msr4 msr3 msr2 msr1 msr0 r/w r r r r r/w r/w r/w r/w rtcrst undefined undefined undefined undefined 0 0 0 0 other resets undefined undefined undefined undefined 0 0 0 0 bit name function 7 msr7 dcd1# signal status 1 : low level 0 : high level 6 msr6 ri signal (internal) status 1 : low level 0 : high level 5 msr5 dsr1# input status 1 : low level 0 : high level 4 msr4 cts1# input status 1 : low level 0 : high level 3 msr3 dcd1# signal change 1 : changed 0 : no change 2 msr2 ri signal (internal) change 1 : changed 0 : no change 1 msr1 dsr1# signal change 1 : changed 0 : no change 0 msr0 cts1# signal change 1 : changed 0 : no change this register indicates the current status and change in status of various control signals that are input to the cpu from a modem or other peripheral device. the msr(3:0) bits are cleared to 0 if they are read when they are set to 1. chapter 19 serial interface unit 1 (siu1) user ? s manual u14272ej3v0um 376 19.3.12 siusc_1 (0x0c00 0017) bit 76543210 name scr7 scr6 scr5 scr4 scr3 scr2 scr1 scr0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst undefined undefined undefined undefined undefined undefined undefined undefined other resets undefined undefined undefined undefined undefined undefined undefined undefined bit name function 7 to 0 scr(7:0) general-purpose data this register is a readable/writable 8-bit register, and can be used freely by users. it does not affect control of the siu1. 19.3.13 siureset_1 (0x0c00 0019) bit 76543210 name reserved reserved reserved reserved reserved reserved reserved siu reset r/w rrrrrrrr/w rtcrst00000000 other resets00000000 bit name function 7 to 1 reserved 0 is returned when read 0 siureset siu1 reset 1 : reset 0 : release reset this register is used to reset siu1 forcibly. chapter 19 serial interface unit 1 (siu1) user ? s manual u14272ej3v0um 377 19.3.14 siuactmsk_1 (0x0c00 001c) bit 76543210 name reserved reserved rxdmsk rtsmsk dcdmsk dtrmsk reserved txwrmsk r/w r r r/w r/w r/w r/w r/w r/w rtcrst00000000 other resets00000000 bit name function 7, 6 reserved 0 is returned when read 5 rxdmsk mask for notification of change on rxd1 1 : mask 0 : unmask 4 rtsmsk mask for notification of change on rts1# 1 : mask 0 : unmask 3 dcdmsk mask for notification of change on dcd1# 1 : mask 0 : unmask 2 dtrmsk mask for notification of change on dtr1# 1 : mask 0 : unmask 1 reserved write 0 when write. 0 is returned when read 0 txwrmsk mask for notification of transmit buffer write 1 : mask 0 : unmask this register is used to set masks for notification of operation statuses to the activity timer of the siu1. when 1 is set in this register, state transition of the corresponding signals or write to transmit buffer is not notified to the activity timer. chapter 19 serial interface unit 1 (siu1) user ? s manual u14272ej3v0um 378 19.3.15 siuacttmr_1 (0x0c00 001e) bit 76543210 name siutmo7 siutmo6 siutmo5 siutmo4 siutmo3 siutmo2 siutmo1 siutmo0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00000000 other resets00000000 bit name function 7 to 0 siutmo(7:0) siu activity timeout period 11111111 : 255 x 30.5 s 11111110 : 254 x 30.5 s : 01111111 : 127 x 30.5 s : 00000001 : 30.5 s 00000000 : activity timer disabled user?s manual u14272ej3v0um 379 chapter 20 serial interface unit 2 (siu2) 20.1 general the siu2 is a serial interface that conforms to the rs-232-c communication standard and is equipped with two one-channel interfaces, one for transmission and one for reception. this unit can be also used as an interface in the irda format by means of register setting. this unit is functionally compatible with the ns16550 except for the additional clock control logic to permit the 16650 core clock source to be stopped. figure 20-1. siu2 block diagram v r 4181 uart2 irdin/rxd2 irdout/txd2 rts2# activity timer 2 dtr2# dcd2# clk32k seclk_siu uart2_clock siu2 caution no clock is supplied to the siu2 in the initial state. when using the siu2, set the msksiu18m bit of the cmuclkmsk register in the mba host bridge to 1 in advance so that the clock is supplied. 20.2 clock control logic the power of the 16550 core can be managed by monitoring activity on the modem status pins and writes to the transmit buffer. the clock control logic for the 16550 core monitors activity on the four serial interface input signals; rxd2, rts2#, dcd2#, and dtr2#. it also monitors writes to the 16550 transmit buffer. each source has an associated mask bit which prevents a source from causing reset of the activity timer. activity on the rxd2, rts2#, dcd2# and dtr2# inputs is defined as any change of state (high to low or low to high). when no unmasked activity has been detected on any of the inputs, and no writes have occurred to the transmit buffer within the programmed time-out period specified in the activity timer block, the uart2_clock is stopped. the uart2_clock will remain stopped until the activity is detected on the monitored sources. chapter 20 serial interface unit 2 (siu2) user ? s manual u14272ej3v0um 380 20.3 register set the siu2 registers are listed below. table 20-1. siu2 registers physical address lcr7 r/w register symbol function 0x0c00 0000 0 r siurb_2 receive buffer register (read) w siuth_2 transmit holding register (write) 1 r/w siudll_2 divisor latch (least significant byte) register 0x0c00 0001 0 r/w siuie_2 interrupt enable register 1 r/w siudlm_2 divisor latch (most significant byte) register 0x0c00 0002 ? r siuiid_2 interrupt identification register (read) ? w siufc_2 fifo control register (write) 0x0c00 0003 ? r/w siulc_2 line control register 0x0c00 0004 ? r/w siumc_2 modem control register 0x0c00 0005 ? r siuls_2 line status register 0x0c00 0006 ? r/w siums_2 modem status register 0x0c00 0007 ? r/w siusc_2 scratch register 0x0c00 0008 ? r/w siuirsel_2 siu irda select register 0x0c00 0009 ? r/w siureset_2 siu reset register 0x0c00 000a ? r/w siucsel_2 siu echo back control register 0x0c00 000c ? r/w siuactmsk_2 siu activity mask register 0x0c00 000e ? r/w siuadttmr_2 siu activity timer register remark lcr7 is bit 7 of the siulc_2 register. chapter 20 serial interface unit 2 (siu2) user ? s manual u14272ej3v0um 381 20.3.1 siurb_2 (0x0c00 0000: lcr7 = 0, read) bit 76543210 name rxd7 rxd6 rxd5 rxd4 rxd3 rxd2 rxd1 rxd0 r/w rrrrrrrr rtcrst undefined undefined undefined undefined undefined undefined undefined undefined other resets undefined undefined undefined undefined undefined undefined undefined undefined bit name function 7 to 0 rxd(7:0) serial receive data this register stores receive data used in serial communications. to access this register, set the lcr7 bit (bit 7 of the siulc_2 register) to 0. 20.3.2 siuth_2 (0x0c00 0000: lcr7 = 0, write) bit 76543210 name txd7 txd6 txd5 txd4 txd3 txd2 txd1 txd0 r/w wwwwwwww rtcrst undefined undefined undefined undefined undefined undefined undefined undefined other resets undefined undefined undefined undefined undefined undefined undefined undefined bit name function 7 to 0 txd(7:0) serial transmit data this register stores transmit data used in serial communications. to access this register, set the lcr7 bit (bit 7 of the siulc_2 register) to 0. 20.3.3 siudll_2 (0x0c00 0000: lcr7 = 1) bit 76543210 name dll7 dll6 dll5 dll4 dll3 dll2 dll1 dll0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst undefined undefined undefined undefined undefined undefined undefined undefined other resets undefined undefined undefined undefined undefined undefined undefined undefined bit name function 7 to 0 dll(7:0) baud rate divisor (low-order byte) this register is used to set the divisor (division rate) for the baud rate generator. the data in this register and the data in siudlm_2 register as upper 8 bits are together handled as 16-bit data. to access this register, set the lcr7 bit (bit 7 of the siulc_2 register) to 1. chapter 20 serial interface unit 2 (siu2) user ? s manual u14272ej3v0um 382 20.3.4 siuie_2 (0x0c00 0001: lcr7 = 0) bit 76543210 name reserved reserved reserved reserved ie3 ie2 ie1 ie0 r/w r r r r r/w r/w r/w r/w rtcrst00000000 other resets00000000 bit name function 7 to 4 reserved 0 is returned when read 3 ie3 modem status interrupt 1 : enable 0 : prohibit 2 ie2 receive status interrupt 1 : enable 0 : prohibit 1 ie1 transmit holding register empty interrupt 1 : enable 0 : prohibit 0 ie0 receive data ready interrupt or character timeout interrupt in fifo mode 1 : enable 0 : prohibit this register is used to specify interrupt enable/prohibit settings for the five types of interrupt requests used in the siu2. an interrupt is enabled by setting the corresponding bit to 1. overall use of interrupt functions can be halted by setting bits 0 to 3 of this register to 0. when interrupts are prohibited, ? pending ? is not displayed in the iir0 bit in the siuiid_2 register even when interrupt conditions have been met. other functions in the siu2 are not affected even though interrupts are prohibited and the settings in the siuls_2 register and siums_2 register are valid. to access this register, set the lcr7 bit (bit 7 of the siulc_2 register) to 0. chapter 20 serial interface unit 2 (siu2) user ? s manual u14272ej3v0um 383 20.3.5 siudlm_2 (0x0c00 0001: lcr7 = 1) bit 76543210 name dlm7 dlm6 dlm5 dlm4 dlm3 dlm2 dlm1 dlm0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst undefined undefined undefined undefined undefined undefined undefined undefined other resets undefined undefined undefined undefined undefined undefined undefined undefined bit name function 7 to 0 dlm(7:0) baud rate divisor (high-order byte) this register is used to set the divisor (division rate) for the baud rate generator. the data in this register and the data in siudll_2 register as lower 8 bits are together handled as 16-bit data. to access this register, set the lcr7 bit (bit 7 of the siulc_2 register) to 1. the relationship between baud rates and the settings of the siudll_2 and siudlm_2 registers are as follows. chapter 20 serial interface unit 2 (siu2) user ? s manual u14272ej3v0um 384 table 20-2. correspondence between baud rates and divisors baud rate (bps) divisor (dlm(7:0)||dll(7:0)) 1-clock width ( s) 50 23040 20000.00 75 15360 13333.33 110 10473 9090.91 134.5 8565 7434.94 150 7680 6666.67 300 3840 3333.33 600 1920 1666.67 1200 960 833.33 1800 640 555.56 2000 576 500.00 2400 480 416.67 3600 320 277.78 4800 240 208.33 7200 160 138.89 9600 120 104.17 19200 60 52.08 38400 30 26.04 57600 20 17.36 115200 10 8.68 128000 9 7.81 144000 8 6.94 192000 6 5.21 230400 5 4.34 288000 4 3.47 384000 3 2.60 576000 2 1.74 1152000 1 0.868 chapter 20 serial interface unit 2 (siu2) user ? s manual u14272ej3v0um 385 20.3.6 siuiid_2 (0x0c00 0002: read) bit 76543210 name iir7 iir6 reserved reserved iir3 iir2 iir1 iir0 r/w rrrrrrrr rtcrst00000001 other resets00000001 bit name function 7, 6 iir(7:6) becomes 11 when fcr0 bit = 1 5, 4 reserved 0 is returned when read 3 iir3 pending of the character timeout interrupt request (in fifo mode) 1 : no pending 0 : pending 2, 1 iir(2:1) indicates the priority level of interrupts. see the following table. 0 iir0 pending interrupt requests 1 : no pending 0 : pending this register indicates priority levels for interrupts and existence of pending interrupt requests. from highest to lowest priority, the involved interrupts are the receive line status, the receive data ready, the character timeout, the transmit holding register empty, and the modem status. the content of the iir3 bit is valid only in the fifo mode and it is always 0 in the 16450 mode. the iir2 bit becomes 1 when the iir3 bit is set to 1. chapter 20 serial interface unit 2 (siu2) user ? s manual u14272ej3v0um 386 table 20-3. interrupt function siuiid_2 register interrupt set/reset function bit 3 note bit 2 bit 1 priority level interrupt type interrupt source interrupt reset control 0 1 1 highest (1st) receive line status overrun error, parity error, framing error, or break read line status register 0 1 0 2nd receive data ready receive data exists or has reached the trigger level. read the receive buffer register or lower the data in the fifo than trigger level. 1 1 0 2nd character timeout during the time period for the four most recent characters, not one character has been read from the receive fifo nor has a character been input to the receive fifo. during this period, at least one character has been held in the receive fifo. read receive buffer register 0 0 1 3rd transmit holding register empty transmit register is empty read iir (if it is the interrupt source) or write to transmit holding register 0 0 0 4th modem status cts2#, dsr2#, or dcd2# read modem status register note fifo mode only. chapter 20 serial interface unit 2 (siu2) user ? s manual u14272ej3v0um 387 20.3.7 siufc_2 (0x0c00 0002: write) bit 76543210 name fcr7 fcr6 reserved reserved fcr3 fcr2 fcr1 fcr0 r/w ww r r wwww rtcrst00000000 other resets00000000 bit name function 7, 6 fcr(7:6) receive fifo trigger level 11 : 14 bytes 10 : 8 bytes 01 : 4 bytes 00 : 0 bytes 5, 4 reserved 0 is returned when read 3 fcr3 switch between 16450 mode and fifo mode 1 : from 16450 mode to fifo mode 0 : from fifo mode to 16450 mode 2 fcr2 transmit fifo and its counter clear. cleared to 0 when 1 is written. 1 : fifo and its counter clear 0 : normal 1 fcr1 receive fifo and its counter clear. cleared to 0 when 1 is written. 1 : fifo and its counter clear 0 : normal 0 fcr0 receive/transmit fifo enable. cleared to 0 when 1 is written. 1 : enable 0 : disable this register is used to control the fifos. chapter 20 serial interface unit 2 (siu2) user ? s manual u14272ej3v0um 388 ? fifo interrupt modes when receive fifo is enabled and receive interrupt requests are enabled, receive interrupts can occur as described below. 1. when the fifo is reached to the specified trigger level, a receive data ready interrupt request is notified to the cpu. this interrupt is cleared when the fifo goes below the trigger level. 2. when the fifo is reached to the specified trigger level, the siuiid_2 register indicates a receive data ready interrupt request. same as the interrupt above, the suiid_2 register is cleared when the fifo goes below the trigger level. 3. the receive line status interrupt is assigned to a higher priority level than the receive data ready interrupt. 4. when characters are transferred from the shift register to the receive fifo, 1 is set to the lsr0 bit of the siuls_2 register. the value of this bit returns to 0 when the fifo becomes empty. when receive fifo is enabled and receive interrupts are enabled, receive fifo timeout interrupt requests can occur as described below. 1. followings are the conditions under which fifo timeout interrupt requests occur. at least one character is being stored in the fifo. the time required for sending four characters has elapsed since the serial reception of the last character (includes the time for the second stop bit in cases where it is specified that two stop bits are required). the time required for sending four characters has elapsed since the last read of the fifo by the cpu. the time between receiving the last character and issuing a timeout interrupt request is a maximum of 160 ms when operating at 300 baud and receiving 12-bit data. 2. the transfer time for a character is calculated based on the baud rate clock for reception (internal) (which is why the elapsed time is in proportion to the baud rate). 3. once a timeout interrupt request has occurred, the timeout interrupt is cleared and the timer is reset as soon as the cpu reads one character from the receive fifo. 4. if no timeout interrupt request has occurred, the timer is reset when a new character is received or when the cpu reads the receive fifo. chapter 20 serial interface unit 2 (siu2) user ? s manual u14272ej3v0um 389 when transmit fifo is enabled and transmit interrupts are enabled, transmit interrupt requests can occur as described below. 1. when the transmit fifo becomes empty, a transmit holding register empty interrupt request occurs. this interrupt request is cleared when a character is written to the transmit holding register (from one to 16 characters can be written to the transmit fifo during servicing of this interrupt), or when the siuiid_2 register is read. 2. if there are not at least two bytes of character data in the transmit fifo between one time when the lsr5 bit = 1 (transmit fifo is empty) in the siuls_2 register and the next time when the lsr5 bit = 1, transmit fifo empty status is reported to the iir bits after a delay period calculated as ? the time for one character ? the time for the last stop bit(s) ? . when transmit interrupts are enabled, the first transmit interrupt request that occurs after the fcr0 bit (fifo enable bit) in the siufc_2 register is overwritten is indicated immediately. the priority level of the character timeout interrupt and receive fifo trigger level interrupt is the same as that of the receive data ready interrupt. the priority level of the transmit fifo empty interrupt is the same as that of the transmit holding register empty interrupt. whether data to be transmitted exists or not in the transmit fifo and the transmit shift register, check the lsr6 bit of the siuls_2 register. the lsr5 bit of the siuls_2 register is used to check whether data to be transferred exists or not in the transmit fifo only. therefore, there may be data in the transmit shift register. fifo polling mode when the fcr0 bit = 1 (fifo is enabled) in the siufc_2 register, if the value of any or all of the siuie_2 register bits 3 to 0 becomes 0, siu2 enters fifo polling mode. because the transmit block and receive block are controlled separately, polling mode can be set for either or both blocks. when in this mode, the status of the transmit block and/or receive block can be checked by reading the siuls_2 register via a user program. when in the fifo polling mode, there is no notification when the trigger level is reached or when a timeout occurs, but the receive fifo and transmit fifo can still store characters as they normally do. chapter 20 serial interface unit 2 (siu2) user ? s manual u14272ej3v0um 390 20.3.8 siulc_2 (0x0c00 0003) bit 76543210 name lcr7 lcr6 lcr5 lcr4 lcr3 lcr2 lcr1 lcr0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00000000 other resets00000000 bit name function 7 lcr7 divisor latch access register switching 1 : divisor latch access register 0 : receive buffer, transmit holding register, interrupt enable register 6 lcr6 break control 1 : set break 0 : clear break 5 lcr5 parity fixing 1 : fixed parity 0 : parity not fixed 4 lcr4 parity setting 1 : even parity 0 : odd parity 3 lcr3 parity enable 1 : create parity (during transmission) or check parity (during reception) 0 : no parity (during transmission) or no checking (during reception) 2 lcr2 stop bit specification 1 : 1.5 bits (character length is 5 bits) 2 bits (character length is 6, 7, or 8 bits) 0 : 1 bit 1, 0 lcr(1:0) specifies the length of one character (number of bits) 11 : 8 bits 10 : 7 bits 01 : 6 bits 00 : 5 bits this register is used to specify the format for asynchronous data communication and exchange and to set the divisor latch access register. the lcr6 bit is used to send the break status to the receive side ? s uart. when the lcr6 bit = 1, the serial output (txd2) is forcibly set to the spacing (0) state. the setting of the lcr5 bit becomes valid according to settings in the lcr4 and lcr3 bits. chapter 20 serial interface unit 2 (siu2) user ? s manual u14272ej3v0um 391 20.3.9 siumc_2 (0x0c00 0004) bit 76543210 name reserved reserved reserved mcr4 mcr3 mcr2 mcr1 mcr0 r/w r r r r/w r/w r/w r/w r/w rtcrst00000000 other resets00000000 bit name function 7 to 5 reserved 0 is returned when read 4 mcr4 use of diagnostic testing (local loopback) 1 : enable 0 : disable 3 mcr3 out2 signal (internal) setting 1 : low level 0 : high level 2 mcr2 out1 signal (internal) setting 1 : low level 0 : high level 1 mcr1 rts2# output control 1 : low level 0 : high level 0 mcr0 dtr2# output control 1 : low level 0 : high level this register is used to control the interface with a modem or data set (or a peripheral device that emulates a modem). the settings of the mcr3 and mcr2 bits become valid only when the mcr4 bit is set to 1 (enable use of local loopback). local loopback the local loopback can be used to test the transmit/receive data path in siu2. the following operation (local loopback) is executed inside the siu2 when the mcr4 bit = 1. the transmit block ? s serial output (txd2) enters the marking state (1) and the serial input (rxd2) to the receive block is cut off. the transmit shift register ? s output is looped back to the receive shift register ? s input. the four modem control inputs (dsr2#, cts2#, ri (internal), and dcd2#) are cut off and the four modem control outputs (dtr2#, rts2#, out1 (internal), and out2 (internal)) are internally connected to the corresponding modem control inputs. the modem control output pins are forcibly set as inactive (high level). during this kind of loopback mode, transmitted data can be immediately and directly received. when in loopback mode, both transmit and receive interrupts can be used. the interrupt sources are external sources in relation to the transmit and receive blocks. although modem control interrupts can be used, the low- order four bits of the modem control register can be used instead of the four modem control inputs as interrupt sources. as usual, each interrupt is controlled by an interrupt enable register. chapter 20 serial interface unit 2 (siu2) user ? s manual u14272ej3v0um 392 20.3.10 siuls_2 (0x0c00 0005) bit 76543210 name lsr7 lsr6 lsr5 lsr4 lsr3 lsr2 lsr1 lsr0 r/w rrrrrrrr rtcrst01100000 other resets01100000 bit name function 7 lsr7 error detection (fifo mode) 1 : parity error, framing error, or break is detected. 0 : no error 6 lsr6 transmit block empty 1 : no data in transmit holding register and transmit shift register no data in transmit fifo (during fifo mode) 0 : data exists in transmit holding register or transmit shift register data exists in transmit fifo (during fifo mode) 5 lsr5 transmit holding register empty 1 : character is transferred to transmit shift register (during 16450 mode) transmit fifo is empty (during fifo mode) 0 : character is stored in transmit holding register (during 16450 mode) transmit data exists in transmit fifo (during fifo mode) 4 lsr4 break interrupt 1 : detected 0 : no break 3 lsr3 framing error 1 : detected 0 : no error 2 lsr2 parity error 1 : detected 0 : no error 1 lsr1 overrun error 1 : detected (receive data is overwritten) 0 : no error 0 lsr0 receive data ready 1 : receive data exists in fifo 0 : no receive data in fifo the cpu uses this register to get information related to data transfers. when lsr7 and lsr(4:1) bits are 1, reading this register clears these bits to 0. caution the lsr0 bit (receive data ready bit) is set before the serial data reception is completed. therefore, the lsr0 bit may not be cleared if the serial receive data is read from the siurb_2 register immediately after this bit is set. when reading data from the siurb_2 register, wait for the stop bit width time since the lsr0 bit is set. chapter 20 serial interface unit 2 (siu2) user ? s manual u14272ej3v0um 393 lsr7 bit is valid only in fifo mode, and it indicates always 0 in 16450 mode. the value of lsr4 bit becomes 1 when the spacing status (0) of receive data input is held longer than the time required for transmission of one word (start bit + data bits + parity bit + stop bit). when in fifo mode, if a break is detected for one character in the fifo, the character is regarded as an error character and the cpu is notified of a break when that character reaches the highest position in the fifo. when a break occurs, one ? zero ? character is sent to the fifo. when the rxd2 enters marking status, and the next valid start bit is received, the next character can be transmitted. the value of lsr3 bit becomes 1 when a zero (spacing level) stop bit is detected following the final data bit or parity bit. when in fifo mode, if a framing error is detected for one character in the fifo, the character is regarded as an error character and the cpu is notified of a framing error when that character reaches the highest position in the fifo. when a framing error occurs, the siu2 prepares for synchronization again. the next start bit is assumed to be the cause of the framing error and the next data is not accepted until the next start bit has been sampled twice. the value of lsr2 bit becomes 1 when a received character does not satisfy the even or odd parity specified in the lcr4 bit. when in fifo mode, if a parity error is detected for one character within the fifo, the character is regarded as an error character and the cpu is notified of a parity error when that character reaches the highest position in the fifo. the value of lsr1 bit becomes 1 when a character is transferred to the receive buffer register before reading by the cpu and the previous character is lost. when in fifo mode, if the data continues to be transferred to the fifo though it exceeds the trigger level, even after the fifo becomes full an overrun error will not occur until all characters are stored in the shift register. the cpu is notified as soon as an overrun error occurs. the characters in the shift register are overwritten and are not transferred to the fifo. chapter 20 serial interface unit 2 (siu2) user ? s manual u14272ej3v0um 394 20.3.11 siums_2 (0x0c00 0006) bit 76543210 name msr7 msr6 msr5 msr4 msr3 msr2 msr1 msr0 r/w r r r r r/w r/w r/w r/w rtcrst undefined undefined undefined undefined 0 0 0 0 other resets undefined undefined undefined undefined 0 0 0 0 bit name function 7 msr7 dcd2# signal status 1 : low level 0 : high level 6 msr6 ri signal (internal) status 1 : low level 0 : high level 5 msr5 dsr2# input status 1 : low level 0 : high level 4 msr4 cts2# input status 1 : low level 0 : high level 3 msr3 dcd2# signal change 1 : changed 0 : no change 2 msr2 ri signal (internal) change 1 : changed 0 : no change 1 msr1 dsr2# signal change 1 : changed 0 : no change 0 msr0 cts2# signal change 1 : changed 0 : no change this register indicates the current status and change in status of various control signals that are input to the cpu from a modem or other peripheral device. the msr(3:0) bits are cleared to 0 if they are read when they are set to 1. chapter 20 serial interface unit 2 (siu2) user ? s manual u14272ej3v0um 395 20.3.12 siusc_2 (0x0c00 0007) bit 76543210 name scr7 scr6 scr5 scr4 scr3 scr2 scr1 scr0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst undefined undefined undefined undefined undefined undefined undefined undefined other resets undefined undefined undefined undefined undefined undefined undefined undefined bit name function 7 to 0 scr(7:0) general-purpose data this register is a readable/writable 8-bit register, and can be used freely by users. it does not affect control of the siu2. 20.3.13 siuirsel_2 (0x0c00 0008) bit 76543210 name reserved reserved reserved reserved reserved reserved reserved sirsel r/w r r r/w r r/w r/w r r/w rtcrst00000000 other resets00000000 bit name function 7, 6 reserved 0 is returned when read 5 reserved write 0 when write. 0 is returned when read. 4 reserved 0 is returned when read 3, 2 reserved write 0 when write. 0 is returned when read. 1 reserved 0 is returned when read 0 sirsel selects communication format 1 : irda 0 : rs-232-c this register is used to set the siu2 ? s communication format (irda or rs-232-c). to use the irda format, an external irda module must be connected. chapter 20 serial interface unit 2 (siu2) user ? s manual u14272ej3v0um 396 20.3.14 siureset_2 (0x0c00 0009) bit 76543210 name reserved reserved reserved reserved reserved reserved reserved siu reset r/w rrrrrrrr/w rtcrst00000000 other resets00000000 bit name function 7 to 1 reserved 0 is returned when read 0 siureset siu2 reset 1 : reset 0 : release reset this register is used to reset siu2 forcibly. 20.3.15 siucsel_2 (0x0c00 000a) bit 76543210 name reserved reserved reserved reserved reserved reserved reserved siucsel r/w rrrrrrrr/w rtcrst00000000 other resets00000000 bit name function 7 to 1 reserved 0 is returned when read 0 siucsel mask for echo back of irda 1 : mask disabled 0 : mask enabled (echo-back mode) this register is used to specify whether the use of echo back function on irda transmission and reception is enabled. chapter 20 serial interface unit 2 (siu2) user ? s manual u14272ej3v0um 397 20.3.16 siuactmsk_2 (0x0c00 000c) bit 76543210 name reserved reserved rxdmsk rtsmsk dcdmsk dtrmsk reserved txwrmsk r/w r r r/w r/w r/w r/w r/w r/w rtcrst00000000 other resets00000000 bit name function 7, 6 reserved 0 is returned when read 5 rxdmsk mask for notification of change on rxd2 1 : mask 0 : unmask 4 rtsmsk mask for notification of change on rts2# 1 : mask 0 : unmask 3 dcdmsk mask for notification of change on dcd2# 1 : mask 0 : unmask 2 dtrmsk mask for notification of change on dtr2# 1 : mask 0 : unmask 1 reserved write 0 when write. 0 is returned when read 0 txwrmsk mask for notification of transmit buffer write 1 : mask 0 : unmask this register is used to set masks for notification of operation statuses to the activity timer of the siu2. when 1 is set in this register, state transition of the corresponding signals or write to transmit buffer is not notified to the activity timer. chapter 20 serial interface unit 2 (siu2) user ? s manual u14272ej3v0um 398 20.3.17 siuacttmr_2 (0x0c00 000e) bit 76543210 name siutmo7 siutmo6 siutmo5 siutmo4 siutmo3 siutmo2 siutmo1 siutmo0 r/w r/w r/w r/w r/w r/w r/w r/w r/w rtcrst00000000 other resets00000000 bit name function 7 to 0 siutmo(7:0) siu activity timeout period 11111111 : 255 x 30.5 s 11111110 : 254 x 30.5 s : 01111111 : 127 x 30.5 s : 00000001 : 30.5 s 00000000 : activity timer disabled user?s manual u14272ej3v0um 399 chapter 21 lcd controller 21.1 overview the v r 4181 includes an lcd control module that operates on the mba bus under the unified memory architecture (uma) conventions. the frame buffer resides in the main dram memory. this module supports an stn lcd panel. 21.1.1 lcd interface the v r 4181 lcd controller is a uma based controller and uses a part of dram memory as a frame buffer. the lcd controller supports monochrome stn lcd panels having 4-bit data bus interfaces and color stn lcd panels having 8-bit data bus interfaces. when interfacing to a color lcd panel, gpio pins must be allocated to provide the upper nibble of the 8-bit lcd data bus. in monochrome mode, the lcd controller supports 1-bpp (bit per pixel) mode (mono), 2-bpp mode (4 gray levels) and 4-bpp mode (16 gray levels). in color mode, the lcd controller supports 4-bpp mode (16 colors) and 8-bpp mode (256 colors). the lcd controller includes a 256-entry x 18-bit color pallet. in color 8-bpp mode, the pallet is used to select 256 colors out of possible 262,144 colors. the lcd controller can support up to 320 x 320 pixels, and typical lcd panel horizontal/vertical resolutions are as follows. table 21-1. lcd panel resolutions (in pixels, typ.) horizontal resolution vertical resolution 320 320 320 240 320 160 240 320 240 240 240 160 160 320 160 240 160 160 the lcd controller also provides power-on and power-down sequence control for the lcd panel via the vplcd pin, which is for lcd logic power control, and vpbias pin, which is for lcd bias power control. power sequencing is provided to prevent latch-up damage to the panel. the lcd controller may be disabled to allow connection of an external lcdc with integrated frame buffer ram such as nec electronics? pd16661. when the internal lcd controller is disabled by setting the lcdgpmode register in the giu, the shclk, loclk, vplcd, and vpbias pins are redefined as follows: chapter 21 lcd controller user?s manual u14272ej3v0um 400 table 21-2. redefining lcd interface pins when lcd controller is disabled redefined function default function lcdcs# shclk memcs16# loclk vpgpio1 vplcd vpgpio0 vpbias 21.2 lcd module features ? resolutions horizontal: up to 320 pixels (the number of pixels must be multiplies of 8) vertical: up to 320 pixels color: 4 bpp, 8 bpp (up to 256 colors) monochrome: 1 bpp, 2 bpp, 4 bpp (up to 16 gray scale) color palette: 18 bits ? high vertical refresh rates for flicker-free lcd frame modulation the following is a block diagram of the lcd controller. chapter 21 lcd controller user?s manual u14272ej3v0um 401 figure 21-1. lcd controller block diagram mba memory controller bus interface unit ram fifos color lookup pixel modulation mba slave interface lcd registers 256 x 18 palette timing generator gpu i/o pins pixel packing mbagp interface 32 16 16 32 mgclk 6r 6g 6b 1r 1g 1b shift clock load clock flm 32 18 32 mgclk mba clock lcd interrupt request data (4 bits) shift clock load clock flm data (8 bits) data (4 bits) data (4 bits) lcd controller the lcd controller is a slave module of the mba bus. its registers can be accessed via the mba slave interface. the frame data are read from main memory via the memory controller and the mbagp (mba graphic port). chapter 21 lcd controller user ? s manual u14272ej3v0um 402 21.3 lcd controller specification 21.3.1 panel configuration and interface (1) view rectangle and horizontal/vertical blank most parameters of the lcd controller are described using a coordinate system. the x coordinate increases as a point moves to the right. the y coordinate increases as a point moves down. the origin is (0, 0). the size of the bounding box is specified by vtotal and htotal. the point (vtotal ? 1, htotal ? 1) is the box ? s lower right corner and includes the horizontal and vertical blanks. vvisible and hvisible define the view rectangle, and outside of the view rectangle are the horizontal blank and vertical blank. figure 21-2. view rectangle and horizontal/vertical blank origin (0, 0) (hvisible ? ? ? ? ? ? ? ? ? ? caution the following expressions must be satisfied. 1. vtotal vvisible 2. htotal hvisible + 6 chapter 21 lcd controller user ? s manual u14272ej3v0um 403 (2) load clock the edge positions of the load clock, loclk, are programmable. each row in the rectangle specified with (0, 0) and (htotal ? 1, vvisible ? 1) must have two loclk edges. the remaining rows in the frame rectangle form the vertical blank. these rows also have two loclk edges if the dummyl bit of the vrvisibreg register is 1, or none if dummyl bit is 0. the first loclk edge is defined by the lcs(7:0) bits of the ldclkstreg register. the second edge is defined by the lce(7:0) bits of the ldclkendreg register, and is usually inside the horizontal blank. the lppol bit of the lcdctrlreg register controls the directions of toggles. if the lppol bit is 0, the first loclk edge is positive and the second is negative. if the lppol bit is 1, the reverse is true. figure 21-3. position of load clock (loclk) origin (0, 0) (hvisible ? ? ? ? caution the following expression must be satisfied. 1. htotal > lce(7:0) x 2 > lcs(7:0) x 2 chapter 21 lcd controller user ? s manual u14272ej3v0um 404 (3) frame clock the edge positions of the frame clock, flm, are also programmable. there must be exactly two flm edges inside the bounding box. the first flm edge is defined by the flmhs(7:0) bits of the fhstartreg register and the flms(8:0) bits of the fvstartreg register. the location of the first edge is at (flmhs x 2, flms). the second flm edge is defined by the flmhe(7:0) bits of the fhendreg register and the flme(8:0) bits of the fvendreg register. the location of second edge is at (flmhe x 2, flme). if the flmpol bit of the lcdctrlreg register is 0, the first flm edge is positive and the second is negative. if the flmpol bit is 1, the reverse is true. figure 21-4. position of frame clock (flm) origin (0, 0) (hvisible ? ? ? ? caution the following expressions must be satisfied. 1. htotal > flmhe(7:0) x 2 > flmhs(7:0) x 2 2. vtotal > flme(8:0), vtotal > flms(8:0) chapter 21 lcd controller user ? s manual u14272ej3v0um 405 (4) shift clock the shift clock (shclk) edges can be programmed only indirectly. the shclk is also output in rows of the vertical blank if the dummyl bit of the vrvisibreg register is 1. the position of shclk edges are controlled by the panelcolor and pandbus bits of the lcdcfgreg0 register. the sclkpol bit of the lcdctrlreg register determines whether data is latched into the panel on the rising or falling edges. if the sclkpol bit is 0, data is latched on the falling edges. (5) m signal some panels also need a modulation signal, m, to operate properly. the modulation rate is controlled by mod(7:0) bits of the lcdcfgreg0 register. if the mod field is 0, the m signal toggles once per frame. if the mod field is not 0, then the m signal toggles once every rows set in the mod field. the m signal toggles at the position specified in the lce field, the same time as the second loclk edge. when the mod field is 0, the m signal toggles when the loclk latches the flm. (6) vertical retrace interrupt when the lcd controller goes through the vertical blank, a status signal bit vireq of the lcdinrqreg register becomes 1. this signal can be configured to be polled or to generate an interrupt request. to enable the interrupt, set the mvireq bit of the lcdimskreg register to 1. once an interrupt request is generated, writing to the vireq bit clears the interrupt request. however, the state of the vireq bit changes to 0 only after the controller returns to top left corner. note that there is some delay between the controller ? s entering or leaving the vertical blank and the changes in the vireq bit. 21.3.2 controller clocks all lcd controller timing is based on the internal clock hpck. the hpck is derived from the gclk, which is derived from the mba clock (tclock). the frequency of gclk can be equal to, one-half of, or one-quarter of that of the mba clock, depending on the pre-scal(1:0) bits of the lcdcfgreg0 register and the mba clock frequency. the hpck frequency is programmable. in each cycle the hpck is at high level for cycles set in the hpckh(5:0) bits of the lcdcfgreg1 register, and at low level for cycles set in the hpckl(5:0) bits of the lcdcfgreg1 register. the values in hpckh and hpckl fields are not arbitrary. their sum must be at least 5, and the following condition must be satisfied: f-hpck chapter 21 lcd controller user ? s manual u14272ej3v0um 406 21.3.3 palette the col(1:0) bits of the lcdcfgreg0 register indicate the desired color depth. if they are set to 0, then a monochrome image can be displayed on a monochrome panel. if they are set 1, then a 4-shade gray scale image can be displayed on a monochrome panel. if they are set to 2 or 3, then a palette is enabled, and a color panel can be used. the palette has 256 entries. each entry has 18 bits and is 6-6-6 format for the rgb color. to access an entry first store its index in the palindex(7:0) bits of the cpindctreg register, then read from or write to the paldata(17:0) bits of the cpaldatreg register. to accelerate continuous accesses, the palrdi bit or the palwri bit of the cpindctreg register can be set to 1. when the palrdi bit is set to 1, the lcd controller automatically adds 1 to the palindex(7:0) bits of the cpindctreg register after reading from the paldata field; when the palwri bit is set to 1, the lcd controller automatically adds 1 to the palindex(7:0) bits after writing to the paldata field. if the col field is set to 2, then the pixel data provides only the lower half of the palette index. the upper half is provided by the palpage(3:0) bits of the cpindctreg register. together they specify one entry in the palette. finally, the hpck and the gclk must be turned on before the palette is accessed. 21.3.4 frame buffer memory and fifo the frame buffer is linear and supports a packed pixel format. the length of a scan line must be a multiple of 32. the last double word of a scan line need not be completely filled. the pixels are stored in double words. the data format of each double word depends on the color depth, as shown in the following table. bit 31 bit 0 18 19 1a 1b 1c 1d 1e 1f 10 11 12 13 14 15 16 17 08 09 0a 0b 0c 0d 0e 0f 00 01 02 03 04 05 06 07 0c 0d 0e 0f 08 09 0a 0b 04 05 06 07 00 01 02 03 06 07 04 05 02 03 00 01 03 02 01 00 the frame buffer memory starts from the 32-bit address specified by the fbsa(31:0) bits of the fbstadreg1 and fbstadreg2 registers, and ends at the address specified by the fbea(31:0) bits of the fbendadreg1 and fbendadreg2 registers. the fbea field does not necessarily show where the last pixel is stored; but it is the address of the first 32-byte page boundary that follows the memory location where the last pixel is stored, starting from the address set in the fbsa field. for example, if fbsa field is 0x0b00 0408, and the frame buffer occupies 235 bytes, then the fbea field is 0x0b00 0508 (fbsa plus the ceiling of 235/32). data from the frame buffer is burst into the fifo to conserve memory bandwidth. each burst transfers 32 bytes. the fifo is divided into three arrays, and each burst fills exactly one array. bursts can not cross array borders, nor can read from and write to the same array at the same time. when the memory bandwidth is low, the fifo bursts only when there are only the number of double words left to be read that is displayed in the fifoc(2:0) bits of the lcdctrlreg register. if the burst is not fast enough in relation to the refresh rate of the panel image, irreversible image degradation occurs due to a lack of data to be displayed, and an interrupt request is generated. this interrupt request can be polled from the fifooverr bit of the lcdinrqreg register. it can be cleared only by stopping and then restarting controller clocks. because image degradation is a serious problem, the value set to the fifoc field should be carefully selected during development. chapter 21 lcd controller user ? s manual u14272ej3v0um 407 21.3.5 panel power on/off sequence some panels use several power supplies, and these supplies and interface logic signals must be turn on or off in sequences specified by the manufacturers. the lcd controller has signals to control these power supplies. each power supply is controlled via the vpbias or vplcd pin. these pins are connected to a pull-up or pull-down resistor in addition to the power supply. when the power is off, these pins are placed into high impedance, so that the resistor pulls the power supply on/off input to the off state. the power-on/off sequence is started by setting the powerc bit of the pwrconreg2 register. setting this bit to 1 starts the power-on sequence. in the power-on sequence the power supply control pins are brought out of high impedance to a programmed state at a programmed time, and the panel interface signals become active at a programmed time. the following table lists the control pins and the programming register bits. pin power-on time bit power-on state bit vpbias biason(4:0) biascon vplcd vccon(4:0) vccc lcd interface i/fon(4:0) ? chapter 21 lcd controller user ? s manual u14272ej3v0um 408 21.3.6 operation of lcd controller figure 21-5. monochrome panel fpd2 (output) fpd3 (output) w ? ? ? ? ? ? ? ? remark w: panel width (hact(5:0) x 8) the polarity (order of rising and falling edges) of the loclk and the shclk are programmable via the lppol and sclkpol bits. chapter 21 lcd controller user ? s manual u14272ej3v0um 409 figure 21-6. color panel in 8-bit data bus fpd2 (output) fpd3 (output) w ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? remark w: panel width (hact(5:0) x 8) the polarity (order of rising and falling edges) of the loclk and the shclk are programmable via the lppol and sclkpol bits. remark in the color 8-bit data bus mode, fpd(3:0) are for upper 4 bits of the lcd data bus, and fpd(7:4) are for lower 4 bits of the lcd data bus. chapter 21 lcd controller user ? s manual u14272ej3v0um 410 figure 21-7. load clock (loclk) pixel row 01 loclk (output) h ? ? ? ? remark h: panel height (vact) th: panel height + dummy lines (vtotal) remark dummy lines are inserted when needed. for example, some panels can display only 240 lines, but has 242 line cycles. load clock can be deactivated during the dummy lines (see dummyl bit description in 21.4.6 ). figure 21-8. frame clock (flm) pixel row 0 ye flm (output) ys 0 xe xs th ? ? remark ys: y-coordinates of the second flm edge (flms) ye: y-coordinates of the first flm edge (flme) the polarity (order of rising and falling edges) of the flm is programmable via the flmpol bit. chapter 21 lcd controller user ? s manual u14272ej3v0um 411 figure 21-9. lcd timing parameters flm (output) fpd(7:0) (output) shclk (output) loclk (output) t6 t7 ... w ? ? figure 21-10. flm period flm (output) t10 the definitions of parameters shown in the figures are given in the table below. chapter 21 lcd controller user ? s manual u14272ej3v0um 412 table 21-3. lcd controller parameters symbol definition tg gclk period this parameter is not one of the timing parameters, but all timing parameters is calculated based on this. gclk is controlled by the pre-scal field. tg = 1 / (frequency of gclk) t1 shift clock high level width color: t1 = tg x hpckh 4-bit bus monochrome: t1 = tg x (hpckh + hpckl) t2 shift clock cycle color: t2 = tg x (hpckh + hpckl) 4-bit bus monochrome: t2 = tg x (hpckh + hpckl) x 2 t3 panel data setup time color : t3 = tg x hpckh 4-bit bus monochrome: t3 = tg x (hpckh + hpckl) t4 panel data hold time color: t4 = tg x hpckl 4-bit bus monochrome: t4 = tg x (hpckh + hpckl) t5 row cycle time t5 = tg x (hpckh + hpckl) x htot t6 load clock start time t6 = tg x (hpckh + hpckl) x lcs t7 load clock end time t7 = tg x (hpckh + hpckl) x lce t8 flm horizontal start time t8 = tg x (hpckh + hpckl) x flmhs t9 flm horizontal end time t9 = tg x (hpckh + hpckl) x flmhe t10 panel frame period t10 = tg x (hpckh + hpckl) x htot x vtot chapter 21 lcd controller user ? s manual u14272ej3v0um 413 21.4 register set table 21-4. lcd controller registers physical address r/w register symbol function 0x0a00 0400 r/w hrtotalreg horizontal total register 0x0a00 0402 r/w hrvisibreg horizontal visible register 0x0a00 0404 r/w ldclkstreg load clock start register 0x0a00 0406 r/w ldclkendreg load clock end register 0x0a00 0408 r/w vrtotalreg vertical total register 0x0a00 040a r/w vrvisibreg vertical visible register 0x0a00 040c r/w fvstartreg flm vertical start register 0x0a00 040e r/w fvendreg flm vertical end register 0x0a00 0410 r/w lcdctrlreg lcd control register 0x0a00 0412 r/w lcdinrqreg lcd interrupt request register 0x0a00 0414 r/w lcdcfgreg0 lcd configuration register 0 0x0a00 0416 r/w lcdcfgreg1 lcd configuration register 1 0x0a00 0418 r/w fbstadreg1 frame buffer start address 1 register 0x0a00 041a r/w fbstadreg2 frame buffer start address 2 register 0x0a00 0420 r/w fbendadreg1 frame buffer end address 1 register 0x0a00 0422 r/w fbendadreg2 frame buffer end address 2 register 0x0a00 0424 r/w fhstartreg flm horizontal start register 0x0a00 0426 r/w fhendreg flm horizontal end register 0x0a00 0430 r/w pwrconreg1 power control register 1 0x0a00 0432 r/w pwrconreg2 power control register 2 0x0a00 0434 r/w lcdimskreg lcd interrupt mask register 0x0a00 047e r/w cpindctreg color palette index and control register 0x0a00 0480 r/w cpaldatreg color palette data register (32 bits wide) chapter 21 lcd controller user ? s manual u14272ej3v0um 414 21.4.1 hrtotalreg (0x0a00 0400) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr reset 00000000 bit 76543210 name htot7 htot6 htot5 htot4 htot3 htot2 htot1 htot0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 15 to 8 reserved 0 is returned when read 7 to 0 htot(7:0) number of horizontal total columns. set this register to a value one half of the horizontal total. horizontal total = horizontal visible width + horizontal blank 21.4.2 hrvisibreg (0x0a00 0402) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr reset 00000000 bit 76543210 name reserved reserved hact5 hact4 hact3 hact2 hact1 hact0 r/w r r r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 15 to 6 reserved 0 is returned when read 5 to 0 hact(5:0) number of horizontal visible pixels. set this register to a value one eighth of the horizontal visible pixels. chapter 21 lcd controller user ? s manual u14272ej3v0um 415 21.4.3 ldclkstreg (0x0a00 0404) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr reset 00000000 bit 76543210 name lcs7 lcs6 lcs5 lcs4 lcs3 lcs2 lcs1 lcs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 15 to 8 reserved 0 is returned when read 7 to 0 lcs(7:0) x coordinate of the first edge of the loclk. set this register to a value one half of the first edge of the loclk. 21.4.4 ldclkendreg (0x0a00 0406) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr reset 00000000 bit 76543210 name lce7 lce6 lce5 lce4 lce3 lce2 lce1 lce0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 15 to 8 reserved 0 is returned when read 7 to 0 lce(7:0) x coordinate of the second edge of the loclk. set this register to a value one half of the second edge of the loclk. chapter 21 lcd controller user ? s manual u14272ej3v0um 416 21.4.5 vrtotalreg (0x0a00 0408) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved vtot8 r/w rrrrrrrr/w reset 00000000 bit 76543210 name vtot7 vtot6 vtot5 vtot4 vtot3 vtot2 vtot1 vtot0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 15 to 9 reserved 0 is returned when read 8 to 0 vtot(8:0) vertical total number of lines including vertical retrace period 21.4.6 vrvisibreg (0x0a00 040a) bit 151413121110 9 8 name dummyl reserved reserved reserved reserved reserved reserved vact8 r/w r/wrrrrrrr/w reset 00000000 bit 76543210 name vact7 vact6 vact5 vact4 vact3 vact2 vact1 vact0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 15 dummyl dummy line inserting position 0 : immediately before vertical blank 1 : anywhere in vertical blank 14 to 9 reserved 0 is returned when read 8 to 0 vact(8:0) vertical visible number of lines chapter 21 lcd controller user ? s manual u14272ej3v0um 417 21.4.7 fvstartreg (0x0a00 040c) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved flms8 r/w rrrrrrrr/w reset 00000000 bit 76543210 name flms7 flms6 flms5 flms4 flms3 flms2 flms1 flms0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 15 to 9 reserved 0 is returned when read 8 to 0 flms(8:0) y coordinate of the first flm edge 21.4.8 fvendreg (0x0a00 040e) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved flme8 r/w rrrrrrrr/w reset 00000000 bit 76543210 name flme7 flme6 flme5 flme4 flme3 flme2 flme1 flme0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 15 to 9 reserved 0 is returned when read 8 to 0 flme(8:0) y coordinate of the second flm edge chapter 21 lcd controller user ? s manual u14272ej3v0um 418 21.4.9 lcdctrlreg (0x0a00 0410) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr reset 00000000 bit 76543210 name fifoc2 fifoc1 fifoc0 reserved contcke lppol flmpol sclkpol r/w r/w r/w r/w r r/w r/w r/w r/w reset 00000000 bit name function 15 to 8 reserved 0 is returned when read 7 to 5 fifoc(2:0) fifo control. a fifo transfer is performed when only the number of double words set here is left in the fifo. 4 reserved 0 is returned when read 3 contcke lcd controller clock enable 0 : off 1 : on 2 lppol loclk clock polarity 0 : leading edge is rising 1 : leading edge is falling 1 flmpol flm clock polarity 0 : leading edge is rising 1 : leading edge is falling 0 sclkpol shift clock polarity 0 : leading edge is rising (active edge is falling) 1 : leading edge is falling (active edge is rising) chapter 21 lcd controller user ? s manual u14272ej3v0um 419 21.4.10 lcdinrqreg (0x0a00 0412) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr reset 00000000 bit 76543210 name reserved reserved reserved reserved reserved vireq fifoov err reserved r/w rrrrrr/wr/wr reset 00000000 bit name function 15 to 3 reserved 0 is returned when read 2 vireq vertical retrace interrupt request 0 : no request (outside vertical blank) 1 : requested (vertical blank) 1 fifooverr fifo overrun interrupt request 0 : no request 1 : requested 0 reserved 0 is returned when read chapter 21 lcd controller user ? s manual u14272ej3v0um 420 21.4.11 lcdcfgreg0 (0x0a00 0414) bit 151413121110 9 8 name mod7 mod6 mod5 mod4 mod3 mod2 mod1 mod0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit 76543210 name softreset reserved pre-scal1 pre-scal0 col1 col0 panelcolor pandbus r/w r/w r r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 15 to 8 mod(7:0) lcd m signal configuration. these bits specify the number of lines between m toggles. 0 : once per frame 1 : after every line 2 : after every 2 lines : 255 : after every 255 lines 7 softreset software reset for lcd controller. the software reset is active only in test mode. 0 : normal operation 1 : reset 6 reserved 0 is returned when read 5, 4 pre-scal(1:0) gclk (clock for lcd controller) pre-scalar mode to the mba clock 00 : divide by 1 01 : divide by 2 10 : divide by 4 11 : rfu 3, 2 col(1:0) color depth selection 00 : 1 bit (black and white for monochrome panel) 01 : 2 bits (4 gray scale for monochrome panel) 10 : 4 bits (16 gray scale for monochrome or 16 colors for color panel) 11 : 8 bits (256 colors for color panel) 1 panelcolor color/monochrome selection 0 : color 1 : monochrome 0 pandbus panel data width 0 : 4 bits 1 : 8 bits (for dual scan panel or for 8-bit high scan) remark in the 4 bpp mode (16 gray scale) for monochrome panels, the blue area of the color palette is used for displaying. the palette is not used in the other modes (1 bpp and 2 bpp) for monochrome panels. chapter 21 lcd controller user ? s manual u14272ej3v0um 421 21.4.12 lcdcfgreg1 (0x0a00 0416) bit 151413121110 9 8 name reserved reserved hpckl5 hpckl4 hpckl3 hpckl2 hpckl1 hpckl0 r/w r r r/w r/w r/w r/w r/w r/w reset 00000000 bit 76543210 name reserved reserved hpckh5 hpckh4 hpckh3 hpckh2 hpckh1 hpckh0 r/w r r r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 15, 14 reserved 0 is returned when read 13 to 8 hpckl(5:0) number of gclk cycles for hpck low level width 7, 6 reserved 0 is returned when read 5 to 0 hpckh(5:0) number of gclk cycles for hpck high level width chapter 21 lcd controller user ? s manual u14272ej3v0um 422 21.4.13 fbstadreg1 (0x0a00 0418) bit 151413121110 9 8 name fbsa15 fbsa14 fbsa13 fbsa12 fbsa11 fbsa10 fbsa9 fbsa8 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit 76543210 name fbsa7 fbsa6 fbsa5 fbsa4 fbsa3 fbsa2 fbsa1 fbsa0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 15 to 0 fbsa(15:0) frame buffer start address (lower 16 bits) caution fbsa(2:0) bits must be cleared to 0. 21.4.14 fbstadreg2 (0x0a00 041a) bit 151413121110 9 8 name fbsa31 fbsa30 fbsa29 fbsa28 fbsa27 fbsa26 fbsa25 fbsa24 r/w r r r r/w r/w r/w r/w r/w reset 00000000 bit 76543210 name fbsa23 fbsa22 fbsa21 fbsa20 fbsa19 fbsa18 fbsa17 fbsa16 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 15 to 0 fbsa(31:16) frame buffer start address (upper 16 bits) fbsa(31:29) are always 0 when read. the fbstadreg1 and fbstadreg2 registers are used to specify the frame buffer starting address. the frame buffer is linear and the pixels are packed. this address corresponds to the first, top left pixel of the screen. chapter 21 lcd controller user ? s manual u14272ej3v0um 423 21.4.15 fbendadreg1 (0x0a00 0420) bit 151413121110 9 8 name fbea15 fbea14 fbea13 fbea12 fbea11 fbea10 fbea9 fbea8 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit 76543210 name fbea7 fbea6 fbea5 fbea4 fbea3 fbea2 fbea1 fbea0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 15 to 0 fbea(15:0) frame buffer end address (lower 16 bits) 21.4.16 fbendadreg2 (0x0a00 0422) bit 151413121110 9 8 name fbea31 fbea30 fbea29 fbea28 fbea27 fbea26 fbea25 fbea24 r/w r r r r/w r/w r/w r/w r/w reset 00000000 bit 76543210 name fbea23 fbea22 fbea21 fbea20 fbea19 fbea18 fbea17 fbea16 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 15 to 0 fbea(31:16) frame buffer end address (upper 16 bits) fbea(31:29) are always 0 when read. chapter 21 lcd controller user ? s manual u14272ej3v0um 424 21.4.17 fhstartreg (0x0a00 0424) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr reset 00000000 bit 76543210 name flmhs7 flmhs6 flmhs5 flmhs4 flmhs3 flmhs2 flmhs1 flmhs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 15 to 8 reserved 0 is returned when read 7 to 0 flmhs(7:0) x coordinate of the first flm edge. set this register to a value one half of the first edge of flm. 21.4.18 fhendreg (0x0a00 0426) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr reset 00000000 bit 76543210 name flmhe7 flmhe6 flmhe5 flmhe4 flmhe3 flmhe2 flmhe1 flmhe0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 15 to 8 reserved 0 is returned when read 7 to 0 flmhe(7:0) x coordinate of the second flm edge. set this register to a value one half of the second edge of flm. chapter 21 lcd controller user ? s manual u14272ej3v0um 425 21.4.19 pwrconreg1 (0x0a00 0430) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w r r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit 76543210 name reserved reserved reserved biason4 biason3 biason2 biason1 biason0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 15 reserved 0 is returned when read 14 to 5 reserved write 0 when write. 0 is returned when read 4 to 0 biason(4:0) frame at which the bias voltage is turned on chapter 21 lcd controller user ? s manual u14272ej3v0um 426 21.4.20 pwrconreg2 (0x0a00 0432) bit 151413121110 9 8 name testmode vccc reserved reserved biascon powerc i/fon4 i/fon3 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit 76543210 name i/fon2 i/fon1 i/fon0 vccon4 vccon3 vccon2 vccon1 vccon0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 15 testmode test mode enable 0 : normal operation 1 : enters test mode 14 vccc vcc (vplcd) signal polarity control 0 : active low 1 : active high 13, 12 reserved write 0 when write. 0 is returned when read 11 biascon bias (vpbias) signal polarity control 0 : active low 1 : active high 10 powerc power control 0 : off 1 : on 9 to 5 i/fon(4:0) frame at which the panel logic interface signals are turned on 4 to 0 vccon(4:0) frame at which the panel vcc is turned on chapter 21 lcd controller user ? s manual u14272ej3v0um 427 21.4.21 lcdimskreg (0x0a00 0434) bit 151413121110 9 8 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr reset 00000000 bit 76543210 name reserved reserved reserved reserved reserved mvireq mfifo overr reserved r/w rrrrrr/wr/wr reset 00000000 bit name function 15 to 3 reserved 0 is returned when read 2 mvireq vertical retrace interrupt mask 0 : mask 1 : unmask 1 mfifooverr fifo overrun interrupt mask 0 : mask 1 : unmask 0 reserved 0 is returned when read chapter 21 lcd controller user ? s manual u14272ej3v0um 428 21.4.22 cpindctreg (0x0a00 047e) bit 151413121110 9 8 name palpage3 palpage2 palpage1 palpage0 reserved reserved palrdi palwri r/w r/w r/w r/w r/w r r r/w r/w reset 00000000 bit 76543210 name palindex7 palindex6 palindex5 palindex4 palindex3 palindex2 palindex1 palindex0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 15 to 12 palpage(3:0) palette page select used in 4 bpp mode 11, 10 reserved 0 is returned when read 9 palrdi palette index read status 0 : no change after read 1 : incremented by 1 after read 8 palwri palette index write status 0 : no change after write 1 : incremented by 1 after write 7 to 0 palindex(7:0) palette index remark in the 4 bpp mode (16 gray scale) for monochrome panels, the blue area of the color palette is used for displaying. the palette is not used in the other modes (1 bpp and 2 bpp) for monochrome panels. chapter 21 lcd controller user ? s manual u14272ej3v0um 429 21.4.23 cpaldatreg (0x0a0 0480) bit 3130292827262524 name reserved reserved reserved reserved reserved reserved reserved reserved r/w rrrrrrrr reset 00000000 bit 2322212019181716 name reserved reserved reserved reserved reserved reserved paldata17 paldata16 r/w rrrrrrr/wr/w reset 000000u ndefined undefined bit 151413121110 9 8 name paldata15 paldata14 paldata13 paldata12 paldata11 paldata10 paldata9 paldata8 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset undefined undefined undefined undefined undefined undefined undefined undefined bit 76543210 name paldata7 paldata6 paldata5 paldata4 paldata3 paldata2 paldata1 paldata0 r/w r/w r/w r/w r/w r/w r/w r/w r/w reset undefined undefined undefined undefined undefined undefined undefined undefined bit name function 31 to 18 reserved 0 is returned when read 17 to 0 paldata(17:0) color palette data (6-6-6 format) caution do not change palette data during lcd display. user?s manual u14272ej3v0um 430 chapter 22 pll passive components the v r 4181 requires several external passive components for proper operation, which are connected to vdd_pll as illustrated in figure 22-1. figure 22-1. example of connection of pll passive components vdd_logic vdd_pll gnd_logic v r 4181 r c1 c2 gnd_pll remarks 1. capacitors c1 and c2 and resistor r are mounted on the printed circuit board. 2. since the value for the components depends upon the application system, the optimum values for each system should be decided after repeated experimentation. it is essential to isolate the analog power and ground for the pll circuit (vdd_pll, gnd_pll) from the regular power and ground (vdd_logic, gnd_logic). the following values are an example for each component. r = 100 ? c1 = 0.1 f c2 = 1.0 f since the optimum values for the filter components depend upon the application and the system noise environment, these values should be considered as starting points for further experimentation within your specific application. in addition, the choke (inductor: l ) can be considered for use as an alternative to the resistor ( r ) for use in filtering the power supply. user?s manual u14272ej3v0um 431 chapter 23 coprocessor 0 hazards the v r 4110 cpu core avoids contention of its internal resources by causing a pipeline interlock in such cases as when the contents of the destination register of an instruction are used as a source in the succeeding instruction. therefore, instructions such as nop must not be inserted between instructions. however, interlocks do not occur on the operations related to the cp0 registers and the tlb. therefore, contention of internal resources should be considered when composing a program that manipulates the cp0 registers or the tlb. the cp0 hazards define the number of nop instructions that is required to avoid contention of internal resources, or the number of instructions unrelated to contention. this chapter describes the cp0 hazards. the cp0 hazards of the v r 4110 cpu core are as or less stringent than those of the v r 4000. table 23-1 lists the coprocessor 0 hazards of the v r 4110 cpu core. code that complies with these hazards will run without modification on the v r 4000. the contents of the cp0 registers or the bits in the ?source? column of this table can be used as a source after they are fixed. the contents of the cp0 registers or the bits in the ?destination? column of this table can be available as a destination after they are stored. based on this table, the number of nop instructions required between instructions related to the tlb is computed by the following formula, and so is the number of instructions unrelated to contention: (destination hazard number of a) ? [(source hazard number of b) + 1] as an example, to compute the number of instructions required between an mtc0 and a subsequent mfc0 instruction, this is: 5 ? (3 + 1) = 1 instruction the cp0 hazards do not generate interlocks of pipeline. therefore, the required number of instruction must be controlled by program. chapter 23 coproc essor 0 haz ards user?s manual u14272ej3v0um 432 table 23-1. coprocessor 0 hazards source destination operation source name no. of cycles destination name no. of cycles mtc0 ? cpu general-purpose register 5 mfc0 cpu general-purpose register 3 ? tlbr index, tlb 2 pagemask, entryhi, entrylo0, entrylo1 5 tlbwi tlbwr index or random, pagemask, entryhi, entrylo0, entrylo1 2tlb 5 tlbp pagemask, entryhi 2 index 6 epc or errorepc, tlb 2 eret status 2 status[exl], status[erl] 4 cache index load tag ? taglo, taghi, perr 5 cache index store tag taglo, taghi, perr 3 ? cache hit operations cache line 3 cache line 5 coprocessor usable test status[cu], [ksu], [exl], [erl] 2 ? entryhi[asid], status[ksu], [exl], [erl], [re], config[k0] 2 instruction fetch tlb 2 ? epc, status 4 instruction fetch exception ? cause, badvaddr, context, xcontext 5 interrupts cause[ip], status[im], [ie], [exl], [erl] 2 ? entryhi[asid], status[ksu], [exl], [erl], [re], config[k0], tlb 3 config[ad], [ep] 3 load/store watchhi, watchlo 3 ? load/store exception ? epc, status, cause, badvaddr, context, xcontext 5 tlb shutdown ? status[ts] 2 (inst.), 4 (data) remark brackets indicate a bit name or a field name of registers. chapter 23 coproc essor 0 haz ards user?s manual u14272ej3v0um 433 cautions 1. if the setting of the k0 bit in the config register is changed by executing an mtc0 instruction within the kseg0 or ckseg0 area, the change is reflected one to three instructions later from the mtc0 instruction. 2. the instruction following an mtc0 instruction must not be an mfc0 instruction. 3. the five instructions following an mtc0 instruction for the status register that changes the ksu bit and sets the exl and erl bits may be executed in the new mode, and not kernel mode. this can be avoided by setting the exl bit first, leaving the ksu bit set to kernel, and later changing the ksu bit. 4. if interrupts are disabled by setting the exl bit in the status register with an mtc0 instruction, an interrupt may occur immediately after the mtc0 instruction without change of the contents of the epc register. this can be avoided by clearing the ie bit first, and later setting the exl bit. 5. there must be two non-load, non-cache instructions between a store and a cache instruction directed to the same cache line to be stored. the status during execution of the following instruction for which cp0 hazards must be considered is described below. (1) mtc0 destination: the completion of writing to a destination register (cp0) of mtc0. (2) mfc0 source: the confirmation of a source register (cp0) of mfc0. (3) tlbr source: the confirmation of the status of tlb and the index register before the execution of tlbr. destination: the completion of writing to a destination register (cp0) of tlbr. (4) tlbwi, tlbwr source: the confirmation of a source register of these instructions and registers used to specify a tlb entry. destination: the completion of writing to tlb by these instructions. (5) tlbp source: the confirmation of the pagemask register and the entryhi register before the execution of tlbp. destination: the completion of writing the result of execution of tlbp to the index register. (6) eret source: the confirmation of registers containing information necessary for executing eret. destination: the completion of the processor state transition by the execution of eret. (7) cache index load tag destination: the completion of writing the results of execution of this instruction to the related registers. chapter 23 coproc essor 0 haz ards user?s manual u14272ej3v0um 434 (8) cache index store tag source: the confirmation of registers containing information necessary for executing this instruction. (9) coprocessor usable test source: the confirmation of modes set by the bits of the cp0 registers in the ?source? column. examples 1. after the contents of the cu0 bit of the status register are modified, when accessing the cp0 registers in user mode or when executing an instruction such as tlb instructions, cache instructions, or branch instructions that use the resource of the cp0. 2. when accessing the cp0 registers in the operating mode set in the status register after the ksu, exl, and erl bits of the status register are modified. (10) instruction fetch source: the confirmation of the operating mode and tlb necessary for instruction fetch. examples 1. when changing the operating mode from user to kernel and fetching instructions after the ksu, exl, and erl bits of the status register are modified. 2. when fetching instructions using the modified tlb entry after tlb modification. (11) instruction fetch exception destination: the completion of writing to registers containing information related to the exception when an exception occurs on instruction fetch. (12) interrupts source: the confirmation of registers judging the condition of occurrence of interrupt when an interrupt factor is detected. (13) loads/sores source: the confirmation of the operating mode related to the address generation of load/store instructions, tlb entries, the cache mode set in the k0 bit of the config register, and the registers setting the condition of occurrence of a watch exception. example when loads/stores are executed in the kernel field after changing the mode from user to kernel. (14) load/store exception destination: the completion of writing to registers containing information related to the exception when an exception occurs on load or store operation. (15) tlb shutdown destination: the completion of writing to the ts bit of the status register when a tlb shutdown occurs. chapter 23 coproc essor 0 haz ards user?s manual u14272ej3v0um 435 table 23-2 indicates examples of calculation. table 23-2. calculation example of cp0 hazard and number of instructions inserted destination source contending internal resource number of instructions inserted formula tlbwr/tlbwi tlbp tlb entry 2 5 ? (2 + 1) tlbwr/tlbwi load or store using newly modified tlb tlb entry 1 5 ? (3 + 1) tlbwr/tlbwi instruction fetch using newly modified tlb tlb entry 2 5 ? (2 + 1) mtc0, status [cu] coprocessor instruction that requires the setting of cu status [cu] 2 5 ? (2 + 1) tlbr mfc0 entryhi entryhi 1 5 ? (3 + 1) mtc0 entrylo0 tlbwr/tlbwi entrylo0 2 5 ? (2 + 1) tlbp mfc0 index index 2 6 ? (3 + 1) mtc0 entryhi tlbp entryhi 2 5 ? (2 + 1) mtc0 epc eret epc 2 5 ? (2 + 1) mtc0 status eret status 2 5 ? (2 + 1) mtc0 status [ie] note instruction that causes an interrupt status [ie] 2 5 ? (2 + 1) note the number of hazards is undefined if the instruction execution sequence is changed by exceptions. in such a case, the minimum number of hazards until the ie bit value is confirmed may be the same as the maximum number of hazards until an interrupt request occurs that is pending and enabled. remark brackets indicate a bit name or a field name of registers. user?s manual u14272ej3v0um 436 appendix a restrictions on v r 4181 a.1 rstsw# during haltimer operation the v r 4181 ignores the rstsw# signal even if it is asserted while the haltimer is operating (counting). if the v r 4181 is started while the rstsw# signal is low, the rstsw reset sequence is not executed and the v r 4181 continues operating until the haltimer is reset. consequently, the operation of the v r 4181 may differ from the operation of the external peripheral circuits when the rstsw# signal is used as a reset signal to the external peripheral circuits. particularly, when the reset signal to a flash memory that includes a boot vector and the rstsw# signal are shared, the v r 4181 may not be able to read the correct program and hang up for 4 seconds between when the v r 4181 is started and when the haltimer is shut down. [workaround] do not share the reset signal to the external peripheral circuits with the rstsw# signal. however, if it is necessary to do so, insert a circuit like the one shown in the figure below to mask the rstsw# signal between when the v r 4181 is started and when the haltimer is cleared, by using the gpio pin. figure a-1. mask circuit for rstsw# signal rstsw# signal (original) mask control (gpio, etc.) rstsw# signal (for actual use) to the v r 4181, flash memory, and external peripheral circuits appendix a restrictions on v r 4181 user ? s manual u14272ej3v0um 437 a.2 rstsw# in hibernate mode the v r 4181 may release the self-refresh mode of dram when the rstsw# signal is asserted in the hibernate mode. as a result, the dram data may be lost. (1) with edo dram when the rstsw# signal goes low, the ras# and cas# signals go high and the self-refresh mode is released. after that dram returns to the self-refresh mode. at this time, the following phenomena may occur, and the dram data may be lost. ? dram is in the normal operation mode while the ras# signal is high ((a) in figure a-2) but a cbr refresh is not executed. ? the high-level output of the cas# signal ((b) in figure a-2) may be a spike. figure a-2. release of self-refresh mode by rstsw# signal (edo dram) ras(1:0)# (output) (a) lcas#, ucas# (output) exit self-refresh mode resume self-refresh mode rstsw# (input) rtc (internal) (b) (c) pulse width: (a) 30 to 60 s (b) 0 (spike) to 30 s (c) 30 s appendix a restrictions on v r 4181 user ? s manual u14272ej3v0um 438 (2) with sdram when the rstsw# signal goes low, the clken (cke) signal goes high. while the clken signal is high, the self-refresh mode of sdram may be released. however, because the sdclk signal is kept low, this problem does not occur in sdram that requires the rising edge of the sdclk signal to release the self-refresh mode. figure a-3. release of self-refresh mode by rstsw# signal (sdram) clken (output) sdclk (output) l rstsw# (input) rtc (internal) sdcs(1:0)# (output) sdras# (output) cas# (output) [workaround] mask the rstsw# signal via an external circuit using the mpower signal and gpio pin, so that the rstsw# signal does not go low in the hibernate mode. user?s manual u14272ej3v0um 439 appendix b index numerics 16450 mode ......................................368, 373, 387, 392 a activation factor.................................................194, 328 compactflash interrupt request............................196 dcd interrupt request ...........................................198 elapsedtime interrupt request ..............................200 gpio activation interrupt request..........................197 power switch interrupt request ..............................195 a/d converter ....................................................275, 301 a/d port scan ............................................................298 address spaces...................................................92, 109 addressing ..................................................................40 addressing modes.......................................................78 adwinenreg .........................................................340 aiu ............................................................................301 operation sequence...............................................315 aiu registers .............................................................302 aiudmamskreg.....................................................149 aiuintreg ..............................................................183 alternate functions ....................................106, 236, 238 audio interface signals ................................................56 audio interface unit ...................................................301 auto-load mode .........................................................142 auto scan mode ........................................................318 auto-stop mode .........................................................142 b badvaddr register.......................................................74 battery monitor interface signals .................................55 battinh shutdown ..................................................193 baud rate...........................................................365, 384 bcucntreg1 .........................................................111 bcurfcntreg.......................................................115 bcuspeedreg.......................................................113 bpp ......................................................................34, 399 bus control ................................................................108 bus control registers .................................................110 bus cycles (16 bits) ...................................................242 bus interface ...............................................................31 bus size.....................................................................352 c cache.................................................................. 44, 106 cache algorithm.......................................................... 71 cache error register ................................................... 87 card (compactflash)........................................ 350, 352 detection ....................................................... 338, 347 status change ............................................... 338, 347 cause register ............................................................ 79 cdstchgreg ........................................................ 338 cfg_reg_1 ............................................................ 333 clkspeedreg....................................................... 117 clock control ..................................................... 360, 379 clock interface ............................................................ 47 clock interface signals ................................................ 55 clock oscillator............................................................ 48 clock supply.............................................................. 106 clocked serial interface unit.............................. 156, 238 cmuclkmsk........................................................... 112 cold reset................................................................ 104 color panel........................................................ 409, 420 compactflash controller .......................................... 328 compactflash interface signals ................................. 56 compare register........................................................ 76 config register ............................................................ 83 context register .......................................................... 71 conversion rate................................................. 308, 314 coprocessor 0 .................................................... 67, 106 coprocessor 0 hazards ............................................ 431 count register............................................................. 74 cp0 ............................................................................ 67 cp0 registers........................................................ 43, 67 cpaldatreg ......................................................... 429 cpindctreg.......................................................... 428 cpu core.............................................................. 31, 35 cpu registers ............................................................. 37 crdstatreg......................................................... 339 csi ................................................................... 156, 238 csi registers............................................................. 160 csi transfer timing.................................................... 157 csi transfer type ...................................................... 159 csiintmsk.............................................................. 166 csiintstat ............................................................ 167 csilstat ................................................................ 164 csimode................................................................. 161 csirxblen ............................................................. 170 appendix b index user?s manual u14272ej3v0um 440 csirxdata............................................................. 163 csitxblen ............................................................. 169 csitxdata ............................................................. 163 d d/a converter ........................................................... 301 data formats ............................................................... 40 data loss................................................................... 299 davref_setup..................................................... 305 dcu ......................................................................... 142 dcu registers........................................................... 144 deadman?s switch reset .................................... 99, 192 deadman?s switch unit............................................. 230 dma control unit....................................................... 142 dma priority ............................................................. 143 dmactlreg........................................................... 154 dmaitmkreg ......................................................... 155 dmaitrqreg ......................................................... 153 dmarstreg .......................................................... 149 doubleword................................................................. 42 dram data preservation.......................................... 192 dram interface................................................ 128, 201 dram space .............................................................. 95 dramhibctl .......................................................... 215 dsu.......................................................................... 230 register setting flow .............................................. 235 dsu registers........................................................... 230 dsuclrreg........................................................... 233 dsucntreg........................................................... 231 dsusetreg ........................................................... 232 dsutimreg............................................................ 234 dtgenclreg ........................................................ 347 dummy line............................................................... 410 dvalidreg............................................................. 311 e ecmphreg............................................................. 220 ecmplreg ............................................................. 219 ecmpmreg ............................................................ 219 ecu.......................................................................... 328 ecu control registers ............................................... 331 ecu registers........................................................... 334 edo dram ...... 128, 129, 192, 201, 203, 205, 207, 437 edomcytreg........................................................ 131 elapsedtime timer ................................................... 216 endian ........................................................................ 40 entryhi register .......................................................... 75 entrylo register.......................................................... 70 epc register ............................................................... 81 errorepc register ....................................................... 89 etimehreg ............................................................ 218 etimelreg ............................................................. 217 etimemreg ............................................................ 217 exca ........................................................................ 328 exception code ........................................................... 80 external rom connection ............................................................ 119 cycle...................................................................... 125 memory map ......................................................... 118 external system bus space ......................................... 93 f fbendadreg1....................................................... 423 fbendadreg2....................................................... 423 fbstadreg1.......................................................... 422 fbstadreg2.......................................................... 422 fhendreg.............................................................. 424 fhstartreg ......................................................... 424 fifo mode ....................................... 368, 373, 387, 392 flash memory ............................................ 123, 124, 127 flm .......................................................... 404, 410, 411 frame buffer .............................................................. 406 frame clock ....................................................... 404, 410 fullspeed mode .................................................. 45, 190 fvendreg.............................................................. 417 fvstartreg.......................................................... 417 g general-purpose i/o.................................................... 33 general-purpose i/o signals ....................................... 58 general-purpose i/o unit........................................... 236 general-purpose register .................................... 37, 238 giu ........................................................................... 236 giu register .............................................................. 244 gloctrlreg ......................................................... 348 gnd signal ................................................................. 59 gpdathreg ........................................................... 254 gpdatlreg............................................................ 255 gphibsth ............................................................... 263 gphibstl................................................................ 264 gpinten.................................................................. 256 gpintmsk ............................................................... 257 gpintstat ............................................................. 262 gpinttyph ............................................................. 258 gpinttypl.............................................................. 260 gpmd0reg ............................................................. 246 appendix b index user?s manual u14272ej3v0um 441 gpmd1reg..............................................................248 gpmd2reg..............................................................250 gpmd3reg..............................................................252 gpsictl...................................................................265 h halfword ......................................................................42 haltimer..........................................................106, 436 haltimer shutdown .........................................101, 193 hi register ...................................................................37 hibernate mode ..........................................45, 191, 437 entering .........................................................201, 202 exiting............................................................203, 204 horizontal blank.........................................................402 hrtotalreg..........................................................414 hrvisibreg ............................................................414 i icu............................................................................171 icu register...............................................................173 id_rev_reg ...........................................................334 if_stat_reg..........................................................335 index register ..............................................................69 initialization interface ..................................................96 initialization interface signals ......................................55 instruction sets......................................................38, 46 internal bus clock ........................................................31 internal i/o space........................................................94 interrupt control .........................................................172 interrupt control unit ..................................................171 interrupt request................................................171, 243 interval time...............................................285, 286, 326 intmskreg.............................................................332 intreg ....................................................................313 intstatreg ...........................................................331 i/o card .............................................................337, 338 i/o direction control (giu) .........................................238 i/o window ................................................................351 ioadshbnreg (n = 0 or 1) .....................................342 ioadslbnreg (n = 0 or 1) ......................................342 ioctrl_reg ...........................................................341 ioshbnreg (n = 0 or 1) ..........................................343 ioslbnreg (n = 0 or 1) ...........................................343 irda.............................................................32, 395, 396 irda interface signals..................................................58 isa bridge.................................................................137 isabrgctl..............................................................138 isabrgsts .............................................................139 itgenctreg .......................................................... 337 k key press.......................................................... 317, 318 keyboard interface signals ......................................... 56 keyboard interface unit............................................. 317 keyen ..................................................................... 267 kiu ........................................................................... 317 kiu register .............................................................. 321 kiudatn (n = 0 to 7)................................................ 322 kiuint...................................................................... 327 kiuintreg.............................................................. 184 kiuscanrep .......................................................... 323 kiuscans ............................................................... 324 kiuwki..................................................................... 326 kiuwks ................................................................... 325 l lcd controller .......................................................... 399 lcd controller registers............................................ 413 lcd interface ............................................. 34, 241, 399 lcd interface signals ................................................. 54 lcd panel .......................................................... 34, 399 lcdcfgreg0 ......................................................... 420 lcdcfgreg1 ......................................................... 421 lcdctrlreg ......................................................... 418 lcdgpmode .......................................................... 273 lcdimskreg.......................................................... 427 lcdinrqreg.......................................................... 419 ldclkendreg....................................................... 415 ldclkstreg ......................................................... 415 led .......................................................................... 353 operation flow ....................................................... 359 led control unit........................................................ 353 led interface signals ................................................. 56 led registers............................................................ 353 ledastcreg ......................................................... 357 ledcntreg ........................................................... 356 ledhtsreg ........................................................... 354 ledintreg............................................................. 358 ledltsreg ............................................................ 355 little endian ................................................................. 40 lladdr register........................................................... 84 lo register.................................................................. 37 load clock ......................................................... 403, 410 local loopback .................................................. 372, 391 loclk.............................................................. 403, 410 appendix b index user?s manual u14272ej3v0um 442 m m signal.................................................................... 405 maiuintreg........................................................... 186 manual scan mode................................................... 318 mba address space ................................................. 109 mba bus................................................................... 108 host bridge........................................................... 108 mcntreg ............................................................... 310 mcnvc_end........................................................... 314 mdmadatreg ....................................................... 304 memcfg_reg........................................................ 133 memoffhnreg (n = 0 to 4) ................................... 346 memofflnreg (n = 0 to 4).................................... 346 memory card .................................................... 337, 338 memory controller ............................................ 106, 131 memory management .......................................... 44, 91 memory mapping ............................................. 118, 350 memory window ....................................................... 350 memselnreg (n = 0 to 4) ...................................... 345 memwidnreg (n = 0 to 4)...................................... 344 micdest1reg1 ..................................................... 145 micdest1reg2 ..................................................... 145 micdest2reg1 ..................................................... 146 micdest2reg2 ..................................................... 146 micdmacfgreg ................................................... 151 micrclenreg....................................................... 150 microphone ...................................................... 301, 316 midatreg .............................................................. 309 mips iii instructions ................................................... 38 mips16 instructions ................................................... 39 miscregn (n = 0 to 15) .......................................... 274 mixed memory mode................................................ 129 mkiuintreg........................................................... 187 mode_reg............................................................. 135 monochrome panel .......................................... 408, 420 mpiuintreg........................................................... 185 msysint1reg........................................................ 176 msysint2reg........................................................ 181 n nmireg ................................................................... 178 o operating modes ........................................................ 78 ordinary rom........................................... 114, 120, 125 p pagerom......................................... 114, 121, 122, 126 page sizes .................................................................. 72 pagemask register...................................................... 72 palette....................................................... 406, 428, 429 parity error register .................................................... 87 pc............................................................................... 37 pclk .................................................................. 47, 138 pclock .................................................... 31, 47, 57, 117 pcs0hia .................................................................. 269 pcs0stpa............................................................... 268 pcs0stra............................................................... 268 pcs1hia .................................................................. 271 pcs1stpa............................................................... 270 pcs1stra............................................................... 270 pcsmode................................................................ 272 physical address......................................................... 92 pin functions ............................................................... 52 configuration ........................................................... 50 connection .............................................................. 63 i/o circuit........................................................... 63, 66 status ...................................................................... 60 pipeline ....................................................................... 44 pipeline clock.............................................................. 31 piu............................................................................ 275 piu registers............................................................. 280 piuabnreg (n = 0 to 3)........................................... 294 piuamskreg.......................................................... 291 piuascnreg .......................................................... 289 piucivlreg ............................................................ 292 piucmdreg............................................................ 287 piucntreg............................................................. 281 piuintreg .............................................................. 284 piupbnmreg (n = 0 or 1, m = 0 to 4) ..................... 293 piusivlreg ............................................................ 285 piustblreg ........................................................... 286 pixel .................................................................... 34, 399 pll passive component ........................................... 430 pmu.......................................................................... 188 pmu registers........................................................... 208 pmucntreg........................................................... 211 pmudivreg ............................................................ 214 pmuintreg ............................................................ 209 pmuwaitreg ......................................................... 213 polling mode ..................................................... 370, 389 power management unit ........................................... 188 power modes ................................................ 31, 45, 188 transition ............................................................... 189 appendix b index user?s manual u14272ej3v0um 443 power-on control .......................................................194 power-on sequence ..........................................102, 407 prid register ...............................................................82 programmable chip selects .......................................242 pwrconreg1 ........................................................425 pwrconreg2 ........................................................426 pwrrsetdrv.........................................................336 r random register .........................................................69 realtime clock unit .....................................................216 receive fifo .............................................160, 369, 388 receive operation ......................................................156 release detection ......................................................298 reset control ..............................................................191 reset function ..............................................................96 revidreg ...............................................................116 rom interface...........................................................118 rom space .................................................................93 rstsw reset ......................................................98, 192 rtc...........................................................................216 rtc registers............................................................216 rtc reset............................................................97, 191 rtcintreg .............................................................229 rtcl1cnthreg .....................................................224 rtcl1cntlreg......................................................223 rtcl1hreg ............................................................222 rtcl1lreg.............................................................221 rtcl2cnthreg .....................................................228 rtcl2cntlreg......................................................227 rtcl2hreg ............................................................226 rtcl2lreg.............................................................225 rtclong timer..........................................................216 s scan (kiu) .................................................................319 scan sequencer (kiu) .......................................320, 324 scan sequencer (piu) .......................278, 283, 290, 295 sck phase................................................................157 scntreg ................................................................307 scnvc_end ............................................................308 sdclk ................................................................47, 135 sdmadatreg.........................................................303 sdram .....................130, 192, 202, 204, 206, 207, 438 sdtimingreg.........................................................136 seqreg...................................................................312 serial interface ..................................................239, 240 serial interface signals ................................................57 serial interface unit 1 ................................................ 360 serial interface unit 2 ................................................ 379 shclk ..................................................................... 405 shift clock ................................................................. 405 shutdown control ...................................................... 193 siu1 ......................................................................... 360 siu1 registers........................................................... 361 siu2 ......................................................................... 379 siu2 registers........................................................... 380 siuactmsk_1 ........................................................ 377 siuactmsk_2 ........................................................ 397 siuacttmr_1 ........................................................ 378 siuacttmr_2 ........................................................ 398 siucsel_2 .............................................................. 396 siudll_1................................................................. 362 siudll_2................................................................. 381 siudlm_1................................................................ 364 siudlm_2................................................................ 383 siufc_1................................................................... 368 siufc_2................................................................... 387 siuie_1 .................................................................... 363 siuie_2 .................................................................... 382 siuiid_1................................................................... 366 siuiid_2................................................................... 385 siuirsel_2 ............................................................. 395 siulc_1................................................................... 371 siulc_2................................................................... 390 siuls_1 ................................................................... 373 siuls_2 ................................................................... 392 siumc_1.................................................................. 372 siumc_2.................................................................. 391 siums_1 .................................................................. 375 siums_2 .................................................................. 394 siurb_1 .................................................................. 362 siurb_2 .................................................................. 381 siureset_1 ........................................................... 376 siureset_2 ........................................................... 396 siusc_1 .................................................................. 376 siusc_2 .................................................................. 395 siuth_1................................................................... 362 siuth_2................................................................... 381 sodatreg ............................................................. 306 soft reset................................................................. 105 softintreg .......................................................... 179 software shutdown ........................................... 100, 193 speaker ............................................................ 301, 315 spkdmacfgreg ................................................... 152 spkrclenreg ...................................................... 150 appendix b index user?s manual u14272ej3v0um 444 spkrsrc1reg1 .................................................... 147 spkrsrc1reg2 .................................................... 147 spkrsrc2reg1 .................................................... 148 spkrsrc2reg2 .................................................... 148 standby mode .................................................... 45, 190 state (piu) ........................................................ 279, 297 status register ............................................................ 76 stn .................................................................... 34, 399 suspend mode ................................................... 45, 190 entering ........................................................ 205, 206 exiting ................................................................... 207 sysclk ............................................................. 47, 141 sysint1reg........................................................... 174 sysint2reg........................................................... 180 sysmemelnreg (n = 0 to 4) ................................. 345 sysmemslnreg (n = 0 to 4) ................................. 344 system bus interface signals ...................................... 52 system control coprocessor ....................................... 67 t taghi register............................................................. 88 taglo register ............................................................ 88 tclock .................................................... 31, 47, 57, 117 timing parameter ...................................................... 411 tlb............................................................................. 44 touch detection......................................................... 298 touch panel............................................................... 276 touch panel interface signals ..................................... 56 touch panel interface unit ......................................... 275 transmit fifo............................................ 160, 370, 389 transmit operation..................................................... 156 u uma.................................................................... 34, 399 v vdd signals................................................................ 59 vertical blank .................................................... 402, 405 view rectangle........................................................... 402 voltselreg.......................................................... 349 voltsenreg ......................................................... 348 vrtotalreg ......................................................... 416 vrvisibreg............................................................ 416 w wait ........................................................................... 352 wake-up event .................................................... 35, 243 watchhi register ......................................................... 85 watchlo register ........................................................ 85 wired register ............................................................. 73 word............................................................................ 42 x xcontext register........................................................ 86 xisactl................................................................... 140 |
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